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| author | Dave.Wen <dave.wen@sifive.com> | 2019-06-12 05:40:43 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2019-06-12 05:40:43 -0700 |
| commit | ed917594167c8f9e3c6dcac5d218926939a26fbb (patch) | |
| tree | 687910585cfe08d5ed8f018eb294da04f2ad3249 /riscv/processor.h | |
| parent | 12b21b212150f6d6016b4b40bb2717d2ca0a185d (diff) | |
| download | spike-ed917594167c8f9e3c6dcac5d218926939a26fbb.zip spike-ed917594167c8f9e3c6dcac5d218926939a26fbb.tar.gz spike-ed917594167c8f9e3c6dcac5d218926939a26fbb.tar.bz2 | |
rvv: merge the vcsr to ordinary csr and remove the redundant functions
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 7724851..5504d21 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -189,8 +189,6 @@ class vectorUnit_t { } reg_t set_vl(uint64_t regId, reg_t reqVL, reg_t newType); - void set_vcsr(int which, reg_t val); - reg_t get_vcsr(int which); reg_t get_vlen() { return VLEN; } reg_t get_elen() { return ELEN; } |