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| author | Dave.Wen <dave.wen@sifive.com> | 2019-03-27 00:18:07 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2019-03-27 02:16:05 -0700 |
| commit | 310586edb1493997aecbc92de6131780c1a62f5b (patch) | |
| tree | a31c3111b2e5fb1095f04adf2c5011f924672173 /riscv/processor.h | |
| parent | 949d4a79004624021904d2cae073698ab64f3bbf (diff) | |
| download | spike-310586edb1493997aecbc92de6131780c1a62f5b.zip spike-310586edb1493997aecbc92de6131780c1a62f5b.tar.gz spike-310586edb1493997aecbc92de6131780c1a62f5b.tar.bz2 | |
add vmul, sbc, and shift instructions.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 1d068b5..10c4bee 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -92,8 +92,8 @@ struct vectorUnit_t { char reg_referenced[NVPR]; int setvl_count; reg_t reg_mask, vstart, vl, vlmax, vsew; - char vxrm, vxsat, vlmul; - reg_t ELEN, VLEN, SLEN, vtype; + reg_t vxrm, vxsat, vlmul; + reg_t ELEN, VLEN, SLEN, LMUL, vtype; reg_t setVL(reg_t reqVL, reg_t newType); |