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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-06 02:56:41 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-06 02:56:41 -0700 |
| commit | 1c663e193561b14c114ee643c16d49da3f046c6d (patch) | |
| tree | 54f8ac7d73797e0d0faf3343fb34223991c19af2 /riscv/processor.h | |
| parent | dc3a76be4f18731dbd3531b01f2b891b41da7eb1 (diff) | |
| download | spike-1c663e193561b14c114ee643c16d49da3f046c6d.zip spike-1c663e193561b14c114ee643c16d49da3f046c6d.tar.gz spike-1c663e193561b14c114ee643c16d49da3f046c6d.tar.bz2 | |
rvv: remove trailing space
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 3d4c8fd..658459a 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -296,7 +296,7 @@ static int cto(reg_t val) class processor_t : public abstract_device_t { public: - processor_t(const char* isa, const char* varch, simif_t* sim, uint32_t id, + processor_t(const char* isa, const char* varch, simif_t* sim, uint32_t id, bool halt_on_reset=false); ~processor_t(); |