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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-25 22:46:48 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-27 19:50:20 -0800 |
| commit | 859be9833258e14fdda13c2254fdd73e64e9c1b5 (patch) | |
| tree | da02fd905dbbfe9f2faf7a377156a9683f5ee458 /riscv/processor.h | |
| parent | 9c53a160e4f0fbfa9a957f6768d5b42ee723ca58 (diff) | |
| download | spike-859be9833258e14fdda13c2254fdd73e64e9c1b5.zip spike-859be9833258e14fdda13c2254fdd73e64e9c1b5.tar.gz spike-859be9833258e14fdda13c2254fdd73e64e9c1b5.tar.bz2 | |
rvv: change vsetvl[i] to match 0.8 spec
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 4c385c1..51bd6c2 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -201,7 +201,7 @@ class vectorUnit_t { reg_file = 0; } - reg_t set_vl(int regId, reg_t reqVL, reg_t newType); + reg_t set_vl(int rd, int rs1, reg_t reqVL, reg_t newType); reg_t get_vlen() { return VLEN; } reg_t get_elen() { return ELEN; } |