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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-04-10 08:53:40 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-04-10 08:54:00 -0700 |
| commit | b30d26373444a1a4da564008091bdd29291f3ae0 (patch) | |
| tree | 3a65a3c9aeddb115eda58a3ae2bfa26379ab629a /riscv/processor.h | |
| parent | c647e40c0aefa0fc42313cc876ffb7180ebf4696 (diff) | |
| download | spike-b30d26373444a1a4da564008091bdd29291f3ae0.zip spike-b30d26373444a1a4da564008091bdd29291f3ae0.tar.gz spike-b30d26373444a1a4da564008091bdd29291f3ae0.tar.bz2 | |
rvv: simplify register offset calculation
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 3700ab5..b290c18 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -166,9 +166,6 @@ struct vectorUnit_t { T& elt(reg_t vReg, reg_t n){ // this still needs to be adjusted for SLEN != VLEN assert(vsew!=0); - reg_t elts_per_reg = (VLEN >> 3) / (vsew >> 3); - vReg += n / elts_per_reg; // for grouping purpose - n = n % elts_per_reg; reg_referenced[vReg] = 1; #if 0 if (((vReg & reg_mask) != vReg) || (n >= vlmax)){ |