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authorChih-Min Chao <chihmin.chao@sifive.com>2020-01-24 08:34:00 -0800
committerChih-Min Chao <chihmin.chao@sifive.com>2020-02-12 23:08:01 -0800
commit48e08c866979d229bc23af69d720a0d2ce632df8 (patch)
tree02b2141ae35ed2f681a77e935b1bcce04616e3fd /riscv/processor.h
parenta466f2b88aca929df477d4ea29705b7ec42d2e94 (diff)
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rvv: remove duplicate vectorUnit declaration
forget to remove the vectorUnit outside, which has been moved into proccess_t as inner class Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.h')
-rw-r--r--riscv/processor.h61
1 files changed, 3 insertions, 58 deletions
diff --git a/riscv/processor.h b/riscv/processor.h
index d73cf80..5690685 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -152,61 +152,6 @@ struct type_sew_t<64>
using type=int64_t;
};
-class vectorUnit_t {
- public:
- processor_t* p;
- void *reg_file;
- char reg_referenced[NVPR];
- int setvl_count;
- reg_t reg_mask, vlmax, vmlen;
- reg_t vstart, vxrm, vxsat, vl, vtype, vlenb;
- reg_t vediv, vsew, vlmul;
- reg_t ELEN, VLEN, SLEN;
- bool vill;
-
- std::unordered_map<uint32_t, std::unordered_map<uint64_t, bool>> impl_table;
-
- // vector element for varies SEW
- template<class T>
- T& elt(reg_t vReg, reg_t n){
- assert(vsew != 0);
- assert((VLEN >> 3)/sizeof(T) > 0);
- reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T));
- vReg += n / elts_per_reg;
- n = n % elts_per_reg;
-#ifdef WORDS_BIGENDIAN
- // "V" spec 0.7.1 requires lower indices to map to lower significant
- // bits when changing SEW, thus we need to index from the end on BE.
- n ^= elts_per_reg - 1;
-#endif
- reg_referenced[vReg] = 1;
-
- T *regStart = (T*)((char*)reg_file + vReg * (VLEN >> 3));
- return regStart[n];
- }
- public:
-
- void reset();
-
- vectorUnit_t();
-
- ~vectorUnit_t(){
- free(reg_file);
- reg_file = 0;
- }
-
- reg_t set_vl(int rd, int rs1, reg_t reqVL, reg_t newType);
-
- reg_t get_vlen() { return VLEN; }
- reg_t get_elen() { return ELEN; }
- reg_t get_slen() { return SLEN; }
-
- VRM get_vround_mode() {
- return (VRM)vxrm;
- }
-
-};
-
// architectural state of a RISC-V hart
struct state_t
{
@@ -484,6 +429,8 @@ public:
reg_t ELEN, VLEN, SLEN;
bool vill;
+ std::unordered_map<uint32_t, std::unordered_map<uint64_t, bool>> impl_table;
+
// vector element for varies SEW
template<class T>
T& elt(reg_t vReg, reg_t n, bool is_write = false){
@@ -511,9 +458,7 @@ public:
void reset();
- vectorUnit_t(){
- reg_file = 0;
- }
+ vectorUnit_t();
~vectorUnit_t(){
free(reg_file);