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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-05 23:52:54 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-11 19:16:22 -0800 |
| commit | ca318d5766a2c05dd1577ebf201e47d0b5ff3d17 (patch) | |
| tree | 13f9f2e7bdc8244999eb7f6e026a51c0bbd27144 /riscv/processor.h | |
| parent | ac5d4a28980e3f86fee5071b5612bc1a5715edce (diff) | |
| download | spike-ca318d5766a2c05dd1577ebf201e47d0b5ff3d17.zip spike-ca318d5766a2c05dd1577ebf201e47d0b5ff3d17.tar.gz spike-ca318d5766a2c05dd1577ebf201e47d0b5ff3d17.tar.bz2 | |
rvv: remove tail-zero
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 8f1a381..b80131c 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -168,7 +168,7 @@ class vectorUnit_t { reg_t vstart, vxrm, vxsat, vl, vtype; reg_t vediv, vsew, vlmul; reg_t ELEN, VLEN, SLEN; - bool TZ, vill; + bool vill; std::unordered_map<uint32_t, std::unordered_map<uint64_t, bool>> impl_table; |