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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-12 16:57:10 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-17 22:32:32 -0800 |
| commit | 3b72e04485d2d1aafdf57e8803cce9b0e73b1a45 (patch) | |
| tree | a67caf6fa8bc60d7c6e2ab65c3bd4a2c533f3344 /riscv/processor.h | |
| parent | c7afadec08a2422e60de0284e3fa675d88191e9e (diff) | |
| download | spike-3b72e04485d2d1aafdf57e8803cce9b0e73b1a45.zip spike-3b72e04485d2d1aafdf57e8803cce9b0e73b1a45.tar.gz spike-3b72e04485d2d1aafdf57e8803cce9b0e73b1a45.tar.bz2 | |
Add --priv option to control which privilege modes are available
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index b80131c..7972c13 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -307,8 +307,8 @@ static int cto(reg_t val) class processor_t : public abstract_device_t { public: - processor_t(const char* isa, const char* varch, simif_t* sim, uint32_t id, - bool halt_on_reset=false); + processor_t(const char* isa, const char* priv, const char* varch, + simif_t* sim, uint32_t id, bool halt_on_reset=false); ~processor_t(); void set_debug(bool value); @@ -475,8 +475,9 @@ private: friend class clint_t; friend class extension_t; - void parse_varch_string(const char* isa); - void parse_isa_string(const char* isa); + void parse_varch_string(const char*); + void parse_priv_string(const char*); + void parse_isa_string(const char*); void build_opcode_map(); void register_base_instructions(); insn_func_t decode_insn(insn_t insn); |