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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-03-26 23:44:54 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-03-27 07:31:25 -0700 |
| commit | 8869fe6f454273edfce714639a5480e5ea5267cc (patch) | |
| tree | b8f20828c24d30275d508f792718273c1b41172d /riscv/processor.h | |
| parent | 05aad3b74eda365fa4be9c026f9d68a7e0f2fe4f (diff) | |
| download | spike-8869fe6f454273edfce714639a5480e5ea5267cc.zip spike-8869fe6f454273edfce714639a5480e5ea5267cc.tar.gz spike-8869fe6f454273edfce714639a5480e5ea5267cc.tar.bz2 | |
rvv: add mlen for convenient
mlen is the bit lenght of one element in V0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 1dc6f40..35a31f7 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -93,7 +93,7 @@ struct vectorUnit_t { char reg_referenced[NVPR]; int setvl_count; reg_t reg_mask, vstart, vl, vlmax, vsew; - reg_t vxrm, vxsat, vlmul; + reg_t vxrm, vxsat, vlmul, vmlen; reg_t ELEN, VLEN, SLEN, LMUL, vtype; reg_t setVL(reg_t reqVL, reg_t newType); |