debug: refine per-inst difference record

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

1 files changed, 10 insertions, 8 deletions

diff --git a/riscv/processor.h b/riscv/processor.h
index 1eea112..d73cf80 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -204,12 +204,7 @@ class vectorUnit_t {
     VRM get_vround_mode() {
       return (VRM)vxrm;
     }
-};
 
-struct prev_reg_state_t {
-  regfile_t<reg_t, NXPR, false> XPR;
-  regfile_t<freg_t, NFPR, false> FPR;
-  vectorUnit_t VU;
 };
 
 // architectural state of a RISC-V hart
@@ -223,9 +218,6 @@ struct state_t
   regfile_t<reg_t, NXPR, true> XPR;
   regfile_t<freg_t, NFPR, false> FPR;
 
-  // Used when tracing
-  prev_reg_state_t *prev_state;
-
   // control and status registers
   reg_t prv;    // TODO: Can this be an enum instead?
   reg_t misa;
@@ -540,6 +532,16 @@ public:
   };
 
   vectorUnit_t VU;
+
+  //extra record to the instruction writing
+  class prev_reg_state_t {
+    public:
+      regfile_t<reg_t, NXPR, false> XPR;
+      regfile_t<freg_t, NFPR, false> FPR;
+      processor_t::vectorUnit_t VU;
+  };
+
+  prev_reg_state_t *prev_state;
 };
 
 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);