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2020-05-20rvv: wrap vm checkingChih-Min Chao1-14/+8
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20rvv: refine overlapd and align checkingChih-Min Chao1-38/+43
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fix clang compile error wthin FDT parsingScott Beamer2-7/+7
2020-05-19Hardwire mstatus.[sie,spie] to zero if 'S' mode absentUdit Khanna1-3/+2
2020-05-19Implement coarse-grain PMP matching logicAndrew Waterman1-6/+6
2020-05-19Implement CSR read/write behavior for coarse-grain PMPAndrew Waterman2-2/+11
2020-05-19Implement configurable PMP countAndrew Waterman1-6/+16
If no PMPs exist, simply deny access to the registers. If some but not all PMPs exist, the others are hardwired to 0.
2020-05-19Disable PMP checks when configuration includes zero PMP registersAndrew Waterman1-1/+1
2020-05-19Support consuming PMP number and granularity from DTBAndrew Waterman3-0/+37
The feature itself isn't implemented yet.
2020-05-19Rename n_pmp constant to max_pmpAndrew Waterman3-12/+12
2020-05-19fdt: add pmp granularity functionChih-Min Chao2-3/+25
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: add pmp parsing helperChih-Min Chao2-1/+17
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: restructure dtb create and config flowChih-Min Chao3-20/+51
1. pass dtb option from constructor 2. separate dtb generation from rom initialization 3. setup clint base from dtb Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: option: add --dtb option to specify dtb binary fileChih-Min Chao3-2/+25
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: add clint base address parsing helperChih-Min Chao2-0/+65
borrow from OpenSBI Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: import fdt library from OpenSBIChih-Min Chao22-3/+5588
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19Add missing stdexcept importsSchuyler Eldridge2-0/+2
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-19rvv: fix widen checkingChih-Min Chao2-4/+11
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19rvv: store eew and emul to P.VU for unit/stride load/storeChih-Min Chao2-23/+22
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: fix unit/stride emul calculationChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: fix compiler warningChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: fix unit/strided load/store checking ruleChih-Min Chao1-29/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: disasm: add missing .wx formatChih-Min Chao1-1/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: disasm: fix unorder index storeChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: vid's mlen overlap checkingDave.Wen1-1/+1
2020-05-18rvv: MLEN=1 overlappingDave.Wen1-4/+4
2020-05-17rvv: mlen=1 WIPDave.Wen2-4/+5
2020-05-14rvv: disasm: fix amo formatChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: amo: only allow 32/64 bit elementChih-Min Chao2-16/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: add vzext/vsextChih-Min Chao8-0/+44
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: op: reorder vextChih-Min Chao1-18/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: dont't explicit throw exceptionChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14disasm: refine structure nameChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: add lmul=1 (m0) in disasm messageDave.Wen1-19/+17
2020-05-14rvv: fix the fractional lmulDave.Wen3-11/+22
2020-05-13rvv: wrong operation to the fractional LMUL bitDave.Wen1-1/+1
2020-05-13rvv: amo: fix wrong index eewChih-Min Chao27-27/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: change to 0.9amoChih-Min Chao49-102/+254
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: amo pre-0.9Chih-Min Chao14-0/+116
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: fractional_lmul when lmul < 1Dave.Wen5-12/+42
2020-05-13vtype: fix the vta and vma functions and debugging displayDave.Wen4-3/+9
2020-05-13eew: add eewDave.Wen1-8/+17
2020-05-13eew: fix the eew=0 caseDave.Wen2-13/+18
2020-05-12rvv: add ext opcodeChih-Min Chao2-0/+26
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-12rvv: op: change vfunary0 and funary1 func6 fieldChih-Min Chao2-50/+56
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-12rvv: ldst: add missng check for VI_LDChih-Min Chao1-2/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-11rvv: change to 0.9 ldstChih-Min Chao79-516/+696
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-07rvv: add eew and lmul for vle/vse/vleffDave.Wen4-7/+39
2020-05-06fractional_lmul: update the vtype register and alos remove the useless reg_maskDave.Wen1-1/+3
2020-05-04zfh: implementation all instructionsChih-Min Chao37-0/+206
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
generated by cgit v1.1 at 2024-08-07 00:25:32 +0000