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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-14 20:15:24 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-14 20:15:24 -0700 |
| commit | a217338c723d37b52553809e301fcf6ef9937e54 (patch) | |
| tree | 0eae612c5ca7273ff9192de8d357c09955d2dab0 | |
| parent | d382dc8747398d95fd657ff8a36f0a49d97f8acd (diff) | |
| download | spike-a217338c723d37b52553809e301fcf6ef9937e54.zip spike-a217338c723d37b52553809e301fcf6ef9937e54.tar.gz spike-a217338c723d37b52553809e301fcf6ef9937e54.tar.bz2 | |
rvv: dont't explicit throw exception
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 93f1ff0..4361466 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1538,7 +1538,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ P.VU.vemul = ((float)P.VU.veew/P.VU.vsew) * P.VU.vlmul; \ if ((P.VU.vemul > 8 && P.VU.vemul < (1/8)) || \ ((P.VU.veew/P.VU.vemul) != (P.VU.vsew/P.VU.vlmul))) { \ - throw trap_illegal_instruction(0); \ + require(0); \ } |