rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-05-20	rvv: wrap vm checking	Chih-Min Chao	1	-14/+8
2020-05-20	rvv: refine overlapd and align checking	Chih-Min Chao	1	-38/+43
2020-05-19	fix clang compile error wthin FDT parsing	Scott Beamer	2	-7/+7
2020-05-19	Hardwire mstatus.[sie,spie] to zero if 'S' mode absent	Udit Khanna	1	-3/+2
2020-05-19	Implement coarse-grain PMP matching logic	Andrew Waterman	1	-6/+6
2020-05-19	Implement CSR read/write behavior for coarse-grain PMP	Andrew Waterman	2	-2/+11
2020-05-19	Implement configurable PMP count	Andrew Waterman	1	-6/+16
2020-05-19	Disable PMP checks when configuration includes zero PMP registers	Andrew Waterman	1	-1/+1
2020-05-19	Support consuming PMP number and granularity from DTB	Andrew Waterman	3	-0/+37
2020-05-19	Rename n_pmp constant to max_pmp	Andrew Waterman	3	-12/+12
2020-05-19	fdt: add pmp granularity function	Chih-Min Chao	2	-3/+25
2020-05-19	fdt: add pmp parsing helper	Chih-Min Chao	2	-1/+17
2020-05-19	fdt: restructure dtb create and config flow	Chih-Min Chao	3	-20/+51
2020-05-19	fdt: option: add --dtb option to specify dtb binary file	Chih-Min Chao	3	-2/+25
2020-05-19	fdt: add clint base address parsing helper	Chih-Min Chao	2	-0/+65
2020-05-19	fdt: import fdt library from OpenSBI	Chih-Min Chao	22	-3/+5588
2020-05-19	Add missing stdexcept imports	Schuyler Eldridge	2	-0/+2
2020-05-19	rvv: fix widen checking	Chih-Min Chao	2	-4/+11
2020-05-19	rvv: store eew and emul to P.VU for unit/stride load/store	Chih-Min Chao	2	-23/+22
2020-05-18	rvv: fix unit/stride emul calculation	Chih-Min Chao	1	-3/+3
2020-05-18	rvv: fix compiler warning	Chih-Min Chao	1	-1/+1
2020-05-18	rvv: fix unit/strided load/store checking rule	Chih-Min Chao	1	-29/+18
2020-05-18	rvv: disasm: add missing .wx format	Chih-Min Chao	1	-1/+3
2020-05-18	rvv: disasm: fix unorder index store	Chih-Min Chao	1	-1/+1
2020-05-18	rvv: vid's mlen overlap checking	Dave.Wen	1	-1/+1
2020-05-18	rvv: MLEN=1 overlapping	Dave.Wen	1	-4/+4
2020-05-17	rvv: mlen=1 WIP	Dave.Wen	2	-4/+5
2020-05-14	rvv: disasm: fix amo format	Chih-Min Chao	1	-1/+1
2020-05-14	rvv: amo: only allow 32/64 bit element	Chih-Min Chao	2	-16/+1
2020-05-14	rvv: add vzext/vsext	Chih-Min Chao	8	-0/+44
2020-05-14	rvv: op: reorder vext	Chih-Min Chao	1	-18/+18
2020-05-14	rvv: dont't explicit throw exception	Chih-Min Chao	1	-1/+1
2020-05-14	disasm: refine structure name	Chih-Min Chao	1	-3/+3
2020-05-14	rvv: add lmul=1 (m0) in disasm message	Dave.Wen	1	-19/+17
2020-05-14	rvv: fix the fractional lmul	Dave.Wen	3	-11/+22
2020-05-13	rvv: wrong operation to the fractional LMUL bit	Dave.Wen	1	-1/+1
2020-05-13	rvv: amo: fix wrong index eew	Chih-Min Chao	27	-27/+27
2020-05-13	rvv: change to 0.9amo	Chih-Min Chao	49	-102/+254
2020-05-13	rvv: amo pre-0.9	Chih-Min Chao	14	-0/+116
2020-05-13	rvv: fractional_lmul when lmul < 1	Dave.Wen	5	-12/+42
2020-05-13	vtype: fix the vta and vma functions and debugging display	Dave.Wen	4	-3/+9
2020-05-13	eew: add eew	Dave.Wen	1	-8/+17
2020-05-13	eew: fix the eew=0 case	Dave.Wen	2	-13/+18
2020-05-12	rvv: add ext opcode	Chih-Min Chao	2	-0/+26
2020-05-12	rvv: op: change vfunary0 and funary1 func6 field	Chih-Min Chao	2	-50/+56
2020-05-12	rvv: ldst: add missng check for VI_LD	Chih-Min Chao	1	-2/+1
2020-05-11	rvv: change to 0.9 ldst	Chih-Min Chao	79	-516/+696
2020-05-07	rvv: add eew and lmul for vle/vse/vleff	Dave.Wen	4	-7/+39
2020-05-06	fractional_lmul: update the vtype register and alos remove the useless reg_mask	Dave.Wen	1	-1/+3
2020-05-04	zfh: implementation all instructions	Chih-Min Chao	37	-0/+206