zfh: implementation all instructions

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

37 files changed, 206 insertions, 0 deletions

diff --git a/riscv/insns/fadd_h.h b/riscv/insns/fadd_h.h
new file mode 100644
index 0000000..2b646ae
--- /dev/null
+++ b/riscv/insns/fadd_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_add(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;
diff --git a/riscv/insns/fclass_h.h b/riscv/insns/fclass_h.h
new file mode 100644
index 0000000..066a2d2
--- /dev/null
+++ b/riscv/insns/fclass_h.h
@@ -0,0 +1,3 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_RD(f16_classify(f16(FRS1)));
diff --git a/riscv/insns/fcvt_d_h.h b/riscv/insns/fcvt_d_h.h
new file mode 100644
index 0000000..6906fc0
--- /dev/null
+++ b/riscv/insns/fcvt_d_h.h
@@ -0,0 +1,6 @@
+require_extension(EXT_ZFH);
+require_extension('D');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_to_f64(f16(FRS1)));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_d.h b/riscv/insns/fcvt_h_d.h
new file mode 100644
index 0000000..f463dd5
--- /dev/null
+++ b/riscv/insns/fcvt_h_d.h
@@ -0,0 +1,6 @@
+require_extension(EXT_ZFH);
+require_extension('D');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f64_to_f16(f64(FRS1)));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_l.h b/riscv/insns/fcvt_h_l.h
new file mode 100644
index 0000000..39178c2
--- /dev/null
+++ b/riscv/insns/fcvt_h_l.h
@@ -0,0 +1,6 @@
+require_extension(EXT_ZFH);
+require_rv64;
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(i64_to_f16(RS1));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_lu.h b/riscv/insns/fcvt_h_lu.h
new file mode 100644
index 0000000..a872c48
--- /dev/null
+++ b/riscv/insns/fcvt_h_lu.h
@@ -0,0 +1,6 @@
+require_extension(EXT_ZFH);
+require_rv64;
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(ui64_to_f16(RS1));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_q.h b/riscv/insns/fcvt_h_q.h
new file mode 100644
index 0000000..94b0001
--- /dev/null
+++ b/riscv/insns/fcvt_h_q.h
@@ -0,0 +1,6 @@
+require_extension(EXT_ZFH);
+require_extension('Q');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f128_to_f16(f128(FRS1)));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_s.h b/riscv/insns/fcvt_h_s.h
new file mode 100644
index 0000000..eb928e9
--- /dev/null
+++ b/riscv/insns/fcvt_h_s.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f32_to_f16(f32(FRS1)));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_w.h b/riscv/insns/fcvt_h_w.h
new file mode 100644
index 0000000..c082454
--- /dev/null
+++ b/riscv/insns/fcvt_h_w.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(i32_to_f16((int32_t)RS1));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_wu.h b/riscv/insns/fcvt_h_wu.h
new file mode 100644
index 0000000..9f2f5f6
--- /dev/null
+++ b/riscv/insns/fcvt_h_wu.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(ui32_to_f16((uint32_t)RS1));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_h.h b/riscv/insns/fcvt_l_h.h
new file mode 100644
index 0000000..5a1fea8
--- /dev/null
+++ b/riscv/insns/fcvt_l_h.h
@@ -0,0 +1,6 @@
+require_extension(EXT_ZFH);
+require_rv64;
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_RD(f16_to_i64(f16(FRS1), RM, true));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_h.h b/riscv/insns/fcvt_lu_h.h
new file mode 100644
index 0000000..f1454c3
--- /dev/null
+++ b/riscv/insns/fcvt_lu_h.h
@@ -0,0 +1,6 @@
+require_extension(EXT_ZFH);
+require_rv64;
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_RD(f16_to_ui64(f16(FRS1), RM, true));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_q_h.h b/riscv/insns/fcvt_q_h.h
new file mode 100644
index 0000000..8a5f680
--- /dev/null
+++ b/riscv/insns/fcvt_q_h.h
@@ -0,0 +1,6 @@
+require_extension(EXT_ZFH);
+require_extension('Q');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_to_f128(f16(FRS1)));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_h.h b/riscv/insns/fcvt_s_h.h
new file mode 100644
index 0000000..bfa2e91
--- /dev/null
+++ b/riscv/insns/fcvt_s_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_to_f32(f16(FRS1)));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_h.h b/riscv/insns/fcvt_w_h.h
new file mode 100644
index 0000000..fe8bb48
--- /dev/null
+++ b/riscv/insns/fcvt_w_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_RD(sext32(f16_to_i32(f16(FRS1), RM, true)));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_h.h b/riscv/insns/fcvt_wu_h.h
new file mode 100644
index 0000000..bf6648d
--- /dev/null
+++ b/riscv/insns/fcvt_wu_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_RD(sext32(f16_to_ui32(f16(FRS1), RM, true)));
+set_fp_exceptions;
diff --git a/riscv/insns/fdiv_h.h b/riscv/insns/fdiv_h.h
new file mode 100644
index 0000000..a169eae
--- /dev/null
+++ b/riscv/insns/fdiv_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_div(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;
diff --git a/riscv/insns/feq_h.h b/riscv/insns/feq_h.h
new file mode 100644
index 0000000..47e75a5
--- /dev/null
+++ b/riscv/insns/feq_h.h
@@ -0,0 +1,4 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_RD(f16_eq(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;
diff --git a/riscv/insns/fle_h.h b/riscv/insns/fle_h.h
new file mode 100644
index 0000000..9fc5968
--- /dev/null
+++ b/riscv/insns/fle_h.h
@@ -0,0 +1,4 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_RD(f16_le(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;
diff --git a/riscv/insns/flh.h b/riscv/insns/flh.h
new file mode 100644
index 0000000..c887999
--- /dev/null
+++ b/riscv/insns/flh.h
@@ -0,0 +1,3 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_FRD(f16(MMU.load_uint16(RS1 + insn.i_imm())));
diff --git a/riscv/insns/flt_h.h b/riscv/insns/flt_h.h
new file mode 100644
index 0000000..f516a38
--- /dev/null
+++ b/riscv/insns/flt_h.h
@@ -0,0 +1,4 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_RD(f16_lt(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;
diff --git a/riscv/insns/fmadd_h.h b/riscv/insns/fmadd_h.h
new file mode 100644
index 0000000..6551de5
--- /dev/null
+++ b/riscv/insns/fmadd_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(FRS3)));
+set_fp_exceptions;
diff --git a/riscv/insns/fmax_h.h b/riscv/insns/fmax_h.h
new file mode 100644
index 0000000..3d4c40e
--- /dev/null
+++ b/riscv/insns/fmax_h.h
@@ -0,0 +1,4 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_FRD(f16_max(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;
diff --git a/riscv/insns/fmin_h.h b/riscv/insns/fmin_h.h
new file mode 100644
index 0000000..5fb1404
--- /dev/null
+++ b/riscv/insns/fmin_h.h
@@ -0,0 +1,4 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_FRD(f16_min(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;
diff --git a/riscv/insns/fmsub_h.h b/riscv/insns/fmsub_h.h
new file mode 100644
index 0000000..934291f
--- /dev/null
+++ b/riscv/insns/fmsub_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN)));
+set_fp_exceptions;
diff --git a/riscv/insns/fmul_h.h b/riscv/insns/fmul_h.h
new file mode 100644
index 0000000..0152df8
--- /dev/null
+++ b/riscv/insns/fmul_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_mul(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;
diff --git a/riscv/insns/fmv_h_x.h b/riscv/insns/fmv_h_x.h
new file mode 100644
index 0000000..c022508
--- /dev/null
+++ b/riscv/insns/fmv_h_x.h
@@ -0,0 +1,3 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_FRD(f16(RS1));
diff --git a/riscv/insns/fmv_x_h.h b/riscv/insns/fmv_x_h.h
new file mode 100644
index 0000000..5e89c4f
--- /dev/null
+++ b/riscv/insns/fmv_x_h.h
@@ -0,0 +1,3 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_RD(sext32((int16_t)(FRS1.v[0])));
diff --git a/riscv/insns/fnmadd_h.h b/riscv/insns/fnmadd_h.h
new file mode 100644
index 0000000..e4c619e
--- /dev/null
+++ b/riscv/insns/fnmadd_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN)));
+set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_h.h b/riscv/insns/fnmsub_h.h
new file mode 100644
index 0000000..0410c3b
--- /dev/null
+++ b/riscv/insns/fnmsub_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(FRS3)));
+set_fp_exceptions;
diff --git a/riscv/insns/fsgnj_h.h b/riscv/insns/fsgnj_h.h
new file mode 100644
index 0000000..79d50f5
--- /dev/null
+++ b/riscv/insns/fsgnj_h.h
@@ -0,0 +1,3 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_FRD(fsgnj16(FRS1, FRS2, false, false));
diff --git a/riscv/insns/fsgnjn_h.h b/riscv/insns/fsgnjn_h.h
new file mode 100644
index 0000000..ebb4ac9
--- /dev/null
+++ b/riscv/insns/fsgnjn_h.h
@@ -0,0 +1,3 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_FRD(fsgnj16(FRS1, FRS2, true, false));
diff --git a/riscv/insns/fsgnjx_h.h b/riscv/insns/fsgnjx_h.h
new file mode 100644
index 0000000..9310269
--- /dev/null
+++ b/riscv/insns/fsgnjx_h.h
@@ -0,0 +1,3 @@
+require_extension(EXT_ZFH);
+require_fp;
+WRITE_FRD(fsgnj16(FRS1, FRS2, false, true));
diff --git a/riscv/insns/fsh.h b/riscv/insns/fsh.h
new file mode 100644
index 0000000..b9fa4e0
--- /dev/null
+++ b/riscv/insns/fsh.h
@@ -0,0 +1,3 @@
+require_extension(EXT_ZFH);
+require_fp;
+MMU.store_uint16(RS1 + insn.s_imm(), FRS2.v[0]);
diff --git a/riscv/insns/fsqrt_h.h b/riscv/insns/fsqrt_h.h
new file mode 100644
index 0000000..138d572
--- /dev/null
+++ b/riscv/insns/fsqrt_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_sqrt(f16(FRS1)));
+set_fp_exceptions;
diff --git a/riscv/insns/fsub_h.h b/riscv/insns/fsub_h.h
new file mode 100644
index 0000000..43b51cc
--- /dev/null
+++ b/riscv/insns/fsub_h.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_sub(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index bbcba5e..7a9b1d5 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -260,6 +260,44 @@ riscv_insn_ext_d = \
 	fsqrt_d \
 	fsub_d \
 
+riscv_insn_ext_zfh = \
+	fadd_h \
+	fclass_h \
+	fcvt_l_h \
+	fcvt_lu_h \
+	fcvt_d_h \
+	fcvt_h_d \
+	fcvt_h_l \
+	fcvt_h_lu \
+	fcvt_h_q \
+	fcvt_h_s \
+	fcvt_h_w \
+	fcvt_h_wu \
+	fcvt_q_h \
+	fcvt_s_h \
+	fcvt_w_h \
+	fcvt_wu_h \
+	fdiv_h \
+	feq_h \
+	fle_h \
+	flh \
+	flt_h \
+	fmadd_h \
+	fmax_h \
+	fmin_h \
+	fmsub_h \
+	fmul_h \
+	fmv_h_x \
+	fmv_x_h \
+	fnmadd_h \
+	fnmsub_h \
+	fsgnj_h \
+	fsgnjn_h \
+	fsgnjx_h \
+	fsh \
+	fsqrt_h \
+	fsub_h \
+
 riscv_insn_ext_q = \
 	fadd_q \
 	fclass_q \
@@ -688,6 +726,7 @@ riscv_insn_list = \
 	$(riscv_insn_ext_m) \
 	$(riscv_insn_ext_f) \
 	$(riscv_insn_ext_d) \
+	$(riscv_insn_ext_zfh) \
 	$(riscv_insn_ext_q) \
 	$(if $(HAVE_INT128),$(riscv_insn_ext_v),) \
 	$(riscv_insn_priv) \