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| author | Dave.Wen <dave.wen@sifive.com> | 2020-05-14 01:50:57 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2020-05-14 01:50:57 -0700 |
| commit | 96c8268cd19da0e005dc5f61f3351e1af7cadd30 (patch) | |
| tree | c00e678c89e7d81f0e633d59a6a4c2270c57162b | |
| parent | b7eafcad7280ab75a6b11ed4df3bb57c1bea1b1b (diff) | |
| download | spike-96c8268cd19da0e005dc5f61f3351e1af7cadd30.zip spike-96c8268cd19da0e005dc5f61f3351e1af7cadd30.tar.gz spike-96c8268cd19da0e005dc5f61f3351e1af7cadd30.tar.bz2 | |
rvv: fix the fractional lmul
| -rw-r--r-- | riscv/decode.h | 2 | ||||
| -rw-r--r-- | riscv/processor.cc | 25 | ||||
| -rw-r--r-- | spike_main/disasm.cc | 6 |
3 files changed, 22 insertions, 11 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 27a449d..93f1ff0 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -117,7 +117,7 @@ public: uint64_t v_simm5() { return xs(15, 5); } uint64_t v_zimm5() { return x(15, 5); } uint64_t v_zimm11() { return x(20, 11); } - uint64_t v_lmul() { return 1 << x(20, 2); } + uint64_t v_lmul() { return x(20, 2); } uint64_t v_sew() { return 1 << (x(22, 3) + 3); } uint64_t v_frac_lmul() { return x(25, 1); } uint64_t v_width() { return x(12, 3); } diff --git a/riscv/processor.cc b/riscv/processor.cc index b0da161..d140648 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -378,7 +378,7 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT if (vtype != newType){ vtype = newType; vsew = 1 << (BITS(newType, 4, 2) + 3); - vlmul = 1 << BITS(newType, 1, 0); + vlmul = BITS(newType, 1, 0); vemul = vlmul; veew = vsew; fractional_lmul = BITS(newType, 5, 5); @@ -387,14 +387,25 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT vediv = 1 << BITS(newType, 9, 8); if (fractional_lmul) { - vlmax = (VLEN/vsew)/vlmul; - vmlen = 1; - vflmul = 1/(float)vlmul; - vlmul = 1; + switch(vlmul){ + case 3: + vlmul = 2; + break; + case 2: + vlmul = 4; + break; + case 1: + vlmul = 8; + break; + } + vlmax = (VLEN/vsew)/vlmul; + vflmul = 1/(float)vlmul; + vlmul = 1; } else { - vlmax = VLEN/vsew * vlmul; - vmlen = vsew / vlmul; + vlmul = 1 << vlmul; + vlmax = VLEN/vsew * vlmul; } + vmlen = vsew / vlmul; vill = !(vlmul>=1 && vlmul <=8) || vsew > ELEN || vediv != 1 || (newType >> 8) != 0; if (vill) { diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index fbfa869..1faef19 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -327,13 +327,13 @@ struct : public arg_t { if(insn.v_frac_lmul()) { std::string lmul_str = ""; switch(lmul){ - case 2: + case 3: lmul_str = "f2"; break; - case 4: + case 2: lmul_str = "f4"; break; - case 8: + case 1: lmul_str = "f8"; break; default: |