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2023-11-27CSR fields introduced by Zicfilp (#210)Ved Shanbhogue1-0/+8
2023-11-24Merge pull request #209 from ved-rivos/zicfissAndrew Waterman2-0/+4
Add CSR fields and SSP CSR introduced by unratified Zicfiss extension
2023-11-24SSP CSR introduced by ZicfissVed Shanbhogue1-0/+1
2023-11-24CSR fields introduced by ZicfissVed Shanbhogue1-0/+3
2023-11-01Merge pull request #206 from ved-rivos/zabhaAndrew Waterman1-0/+23
Add unratified Zabha extension
2023-10-29Add Zabha AMO inst code pointsVed Shanbhogue1-0/+23
2023-10-26Merge pull request #205 from tomhepworth/masterAndrew Waterman1-1/+3
Clarified syntax of regular instructions
2023-10-26Clarified syntax of regular instructionsThomas Hepworth1-1/+3
See https://github.com/riscv/riscv-opcodes/issues/204 Before this change the text implied that bit encodings and variable arguments could not be mixed in the list of instruction arguments. Signed-off-by: Thomas Hepworth <tomhepworth@hotmail.co.uk>
2023-10-20Merge pull request #201 from mehnadnerd/masterAndrew Waterman1-0/+8
Adding Zalasr
2023-10-19Making explicit that the aq bit is set for load-acquire, rl bit is set for ↵brs1-8/+8
store-releasee
2023-10-18Changing it so Zalasr has one bit hardcoded for each, to reduce opcode ↵brs1-8/+8
confusion hopefully
2023-10-18Adding load-acquire/store-release. Note they are written here as `lb.` for ↵brs1-0/+8
the load-acquire byte (so `lb.aq` and `lb.aqrl`), I'm not sure that will work but it passes the tests here.
2023-10-17Add pseudo-instructions for Zimop/Zcmop (#194)Ved Shanbhogue3-51/+114
* add mop.r.N and mop.rr.N pseudo-inst * add c.mop.N pseudo-inst * add arg_lut entries and emitted pseudoops for Zimop/Zcmop * add pseudoinsts for Zimop * add pseudoinsts for Zcmop * update zcmop mnemonics * update zcmop mnemonics
2023-10-17Merge pull request #202 from a4lg/remove-zvamoAndrew Waterman1-41/+0
Remove unratified `Zvamo` instructions from `rv_v`
2023-10-16Remove unratified 'Zvamo' instructions from rv_vTsukasa OI1-41/+0
If this is the only thing happening, I would have just moved those instructions to unratified/rv_zvamo. The reason I didn't is, there is the 'Zabha' extension (containing subword AMO instructions) in the fast track and 8-bit vector AMO instructions conflict with it.
2023-10-09Merge pull request #200 from felixhauptmann/masterAndrew Waterman2-131/+131
Fix artifact generation
2023-10-10fix csv parsingFelix Hauptmann2-131/+131
2023-09-28Merge pull request #198 from sequencer/sdextNeel Gala1-0/+0
rename rv_debug to rv_sdext
2023-09-28rename rv_debug to rv_sdextJiuyang Liu1-0/+0
2023-09-27Merge pull request #197 from sequencer/split_debugAndrew Waterman2-1/+2
split dret from rv_system to rv_debug
2023-09-27split dret from rv_system to rv_debugJiuyang Liu2-1/+2
Because neither priv and unpriv isa mentions dret, and debug is lived in a standalone spec, move dret out from rv_system, while putting it into rv_debug
2023-09-26Merge pull request #195 from sequencer/constant_csvAndrew Waterman5-611/+590
split arg_lut, causes, csr, csr32 from constants.py
2023-09-25split arg_lut, causes, csr, csr32 from constants.pyJiuyang Liu5-611/+590
2023-09-24Merge pull request #196 from sequencer/patch-1Andrew Waterman1-1/+0
Remove duplicate zimm
2023-09-25Remove duplicate zimmJiuyang Liu1-1/+0
Signed-off-by: Jiuyang Liu <liu@jiuyang.me>
2023-09-23Merge pull request #193 from riscv/fix-changes-in-189Neel Gala1-0/+3
retain the original shift instructions as pseudo-ops as well
2023-09-20retain the original shift instructions as pseudo-ops as wellNeel Gala1-0/+3
This is how its done in rv32_i as well.
2023-09-19Merge pull request #192 from sequencer/fix_dupAndrew Waterman1-5/+5
fix instruction duplication between rv128_c and rv64_c
2023-09-20fix instruction duplication between rv128_c and rv64_cJiuyang Liu1-5/+5
2023-09-16Merge pull request #189 from charlie-rivos/support_rv32_shiftAndrew Waterman1-3/+3
Generate compressed shift instructions for rv32
2023-09-16Merge pull request #188 from charlie-rivos/fix_c_addiwAndrew Waterman2-7/+4
C.ADDIW cannot have an rd of 0
2023-09-15Generate compressed shift instructions for rv32Charlie Jenkins1-3/+3
The non-compressed shift instructions have _rv32 versions. Do the same for the compressed shift instructions. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
2023-09-15C.ADDIW cannot have an rd of 0Charlie Jenkins2-7/+4
The code point of rd=0 in C.ADDIW is restricted. Fix formatting while in these files. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
2023-09-15Merge pull request #187 from ved-rivos/zimopAndrew Waterman2-0/+62
Add unratified Zimop and Zcmop extension instructions
2023-09-15add unratified Zcmop instructionsVed Shanbhogue1-0/+13
2023-09-15add unratified Zimop instructionsVed Shanbhogue1-0/+49
2023-08-13Merge pull request #186 from ved-rivos/svadu1Andrew Waterman1-4/+4
Svadu: Rename HADE to ADUE in *envcfg
2023-08-13Svadu: Rename HADE to ADUEVed Shanbhogue1-4/+4
2023-07-31rv64_q_zfa: rs2 is variable field.Nikola Rajovic1-1/+1
2023-07-31rv32_d_zfa: rs2 is variable field.Nikola Rajovic1-1/+1
2023-07-25Merge pull request #181 from rivosinc/add_smcntrpmf_csrsAndrew Waterman1-0/+4
Add Smcntrpmf CSRs
2023-07-25Merge pull request #182 from ↵Andrew Waterman1-8/+8
nrajovic/fix_vector_mask_register_logical_instructions rv_v: fix for Vector Mask-Register Logical instructions.
2023-07-25rv_v: fix for Vector Mask-Register Logical instructions.Nikola Rajovic1-8/+8
- resolves issue #180
2023-07-24Add Smcntrpmf CSRsAtul Khare1-0/+4
Adds mcyclecfg (0x321), minstrefcfg (0x322), mcyclecfgh (0x721), minstretcfgh (0x722).
2023-07-12Merge branch 'rivosinc-smdeleg_definitions'Andrew Waterman2-0/+14
2023-07-12Add Smcdeleg CSR+constantsAtul Khare2-0/+14
Adds CSR scountinhibit (0x120), MSTATEEN0.CD (bit 56), and siselect range (0x40 - 0x5F).
2023-07-10Merge pull request #178 from rivosinc/smcsrind_sscsrind_csrsAndrew Waterman1-0/+15
Add Smcsrind/Sscsrind CSRs
2023-07-10Add Smcsrind/Sscsrind CSRsAtul Khare1-0/+15
Adds mireg2 (0x352), mireg3 (0x353), mireg4 (0x355), mireg5 (0x356), mireg6 (0x357), sireg2 (0x152), sireg3 (0x153), sireg4 (0x155), sireg5 (0x156), sireg6 (0x157), vsireg2 (0x252), vsireg3 (0x253), vsireg4 (0x255), vsireg5 (0x256), vireg6 (0x257).
2023-05-26Merge pull request #177 from liweiwei90/plct-bf16-devNeel Gala1-2/+2
Update encodings for vfwmaccbf16.vv/vf
2023-05-19Update encodings for vfwmaccbf16.vv/vfWeiwei Li1-2/+2
generated by cgit v1.1 at 2024-08-15 23:43:57 +0000