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author | brs <turtwig@utexas.edu> | 2023-10-19 10:45:27 -0500 |
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committer | brs <turtwig@utexas.edu> | 2023-10-19 10:45:27 -0500 |
commit | ce0312a91258aaf6e26e95c90394e45cb9ff4096 (patch) | |
tree | c9ede131f113c64a795aff7ef402ac863cf8f320 | |
parent | 65c40e9167e616431c45d27170a57d572e4ea502 (diff) | |
download | riscv-opcodes-ce0312a91258aaf6e26e95c90394e45cb9ff4096.zip riscv-opcodes-ce0312a91258aaf6e26e95c90394e45cb9ff4096.tar.gz riscv-opcodes-ce0312a91258aaf6e26e95c90394e45cb9ff4096.tar.bz2 |
Making explicit that the aq bit is set for load-acquire, rl bit is set for store-releasee
-rw-r--r-- | unratified/rv_zalasr | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/unratified/rv_zalasr b/unratified/rv_zalasr index 84dbe52..43af470 100644 --- a/unratified/rv_zalasr +++ b/unratified/rv_zalasr @@ -1,8 +1,8 @@ -lb.aq rd rs1 rl 31..27=6 24..20=0 14..12=0 6..2=0x0B 1..0=3 -lh.aq rd rs1 rl 31..27=6 24..20=0 14..12=1 6..2=0x0B 1..0=3 -lw.aq rd rs1 rl 31..27=6 24..20=0 14..12=2 6..2=0x0B 1..0=3 -ld.aq rd rs1 rl 31..27=6 24..20=0 14..12=3 6..2=0x0B 1..0=3 -sb.rl rs1 rs2 aq 31..27=7 14..12=0 11..7=0 6..2=0x0B 1..0=3 -sh.rl rs1 rs2 aq 31..27=7 14..12=1 11..7=0 6..2=0x0B 1..0=3 -sw.rl rs1 rs2 aq 31..27=7 14..12=2 11..7=0 6..2=0x0B 1..0=3 -sd.rl rs1 rs2 aq 31..27=7 14..12=3 11..7=0 6..2=0x0B 1..0=3 +lb.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=0 6..2=0x0B 1..0=3 +lh.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=1 6..2=0x0B 1..0=3 +lw.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=2 6..2=0x0B 1..0=3 +ld.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=3 6..2=0x0B 1..0=3 +sb.rl rs1 rs2 aq 25=1 31..27=7 14..12=0 11..7=0 6..2=0x0B 1..0=3 +sh.rl rs1 rs2 aq 25=1 31..27=7 14..12=1 11..7=0 6..2=0x0B 1..0=3 +sw.rl rs1 rs2 aq 25=1 31..27=7 14..12=2 11..7=0 6..2=0x0B 1..0=3 +sd.rl rs1 rs2 aq 25=1 31..27=7 14..12=3 11..7=0 6..2=0x0B 1..0=3 |