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| author | Andrew Waterman <andrew@sifive.com> | 2023-07-25 16:05:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-25 16:05:34 -0700 |
| commit | 64e0c2f8f062ba9f199215da73c8acb8c3de3055 (patch) | |
| tree | e97ca952965a7091e91757b5c4646d964bc2a7dc | |
| parent | 89420879a12c51de9f0e83a40560b199b5e0fdfd (diff) | |
| parent | a868228adadcfc232475f74891f0cdfb84345652 (diff) | |
| download | riscv-opcodes-64e0c2f8f062ba9f199215da73c8acb8c3de3055.zip riscv-opcodes-64e0c2f8f062ba9f199215da73c8acb8c3de3055.tar.gz riscv-opcodes-64e0c2f8f062ba9f199215da73c8acb8c3de3055.tar.bz2 | |
Merge pull request #182 from nrajovic/fix_vector_mask_register_logical_instructions
rv_v: fix for Vector Mask-Register Logical instructions.
| -rw-r--r-- | rv_v | 16 |
1 files changed, 8 insertions, 8 deletions
@@ -402,14 +402,14 @@ vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57 vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57 vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmandn.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmand.mm 31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmor.mm 31..26=0x1a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmxor.mm 31..26=0x1b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmorn.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmnand.mm 31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmnor.mm 31..26=0x1e vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmxnor.mm 31..26=0x1f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmandn.mm 31..26=0x18 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmand.mm 31..26=0x19 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmor.mm 31..26=0x1a 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmxor.mm 31..26=0x1b 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmorn.mm 31..26=0x1c 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmnand.mm 31..26=0x1d 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmnor.mm 31..26=0x1e 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmxnor.mm 31..26=0x1f 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57 vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57 |