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| author | Neel Gala <neelgala@incoresemi.com> | 2023-09-23 04:40:14 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-23 04:40:14 +0530 |
| commit | 2a95ee78f08437f7847a58a54d81f85633149643 (patch) | |
| tree | 3c3ed20172930b4cc8dc34d82b70e0e6655754df | |
| parent | e7f35d21008dff06634fa8fdba2b5678291a8491 (diff) | |
| parent | 1fed7485d69dc1e5261f46590f015ab20ec02013 (diff) | |
| download | riscv-opcodes-2a95ee78f08437f7847a58a54d81f85633149643.zip riscv-opcodes-2a95ee78f08437f7847a58a54d81f85633149643.tar.gz riscv-opcodes-2a95ee78f08437f7847a58a54d81f85633149643.tar.bz2 | |
Merge pull request #193 from riscv/fix-changes-in-189
retain the original shift instructions as pseudo-ops as well
| -rw-r--r-- | rv32_c | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -1,5 +1,8 @@ # quadrant 1 c.jal c_imm12 1..0=1 15..13=1 +$pseudo_op rv64_c::c.srli c.srli rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0 +$pseudo_op rv64_c::c.srai c.srai rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1 +$pseudo_op rv64_c::c.slli c.slli rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0 $pseudo_op rv64_c::c.srli c.srli_rv32 rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0 $pseudo_op rv64_c::c.srai c.srai_rv32 rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1 $pseudo_op rv64_c::c.slli c.slli_rv32 rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0 |