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| author | Atul Khare <atulkhare@rivosinc.com> | 2023-04-12 18:35:18 -0700 |
|---|---|---|
| committer | Atul Khare <atulkhare@rivosinc.com> | 2023-07-24 17:28:35 -0700 |
| commit | d65b6e76c0ef80ee9a408841566d39c721a0ecd4 (patch) | |
| tree | 7db927faebfda0ee92230877737f2384af05d065 | |
| parent | 89420879a12c51de9f0e83a40560b199b5e0fdfd (diff) | |
| download | riscv-opcodes-d65b6e76c0ef80ee9a408841566d39c721a0ecd4.zip riscv-opcodes-d65b6e76c0ef80ee9a408841566d39c721a0ecd4.tar.gz riscv-opcodes-d65b6e76c0ef80ee9a408841566d39c721a0ecd4.tar.bz2 | |
Add Smcntrpmf CSRs
Adds mcyclecfg (0x321), minstrefcfg (0x322), mcyclecfgh (0x721),
minstretcfgh (0x722).
| -rw-r--r-- | constants.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/constants.py b/constants.py index d345454..6678cff 100644 --- a/constants.py +++ b/constants.py @@ -348,6 +348,8 @@ csrs = [ (0xB1D, 'mhpmcounter29'), (0xB1E, 'mhpmcounter30'), (0xB1F, 'mhpmcounter31'), + (0x321, 'mcyclecfg'), + (0x322, 'minstretcfg'), (0x323, 'mhpmevent3'), (0x324, 'mhpmevent4'), (0x325, 'mhpmevent5'), @@ -455,6 +457,8 @@ csrs32 = [ (0x31E, 'mstateen2h'), # Smstateen (0x31F, 'mstateen3h'), # Smstateen (0x354, 'miph'), + (0x721, 'mcyclecfgh'), + (0x722, 'minstretcfgh'), (0x723, 'mhpmevent3h'), # Sscofpmf (0x724, 'mhpmevent4h'), # Sscofpmf (0x725, 'mhpmevent5h'), # Sscofpmf |