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| author | Jiuyang Liu <liu@jiuyang.me> | 2023-09-27 17:38:40 +0800 |
|---|---|---|
| committer | Jiuyang Liu <liu@jiuyang.me> | 2023-09-27 17:39:08 +0800 |
| commit | 9bb46c8beaf08ebe1f2f69802a31afa9e31af89e (patch) | |
| tree | 1fd8186b3a3c25bfb4fe1cf6ea827e66006ad5ff | |
| parent | 09c6db5a945bd4c8e52f6335591b8cbcedcad155 (diff) | |
| download | riscv-opcodes-9bb46c8beaf08ebe1f2f69802a31afa9e31af89e.zip riscv-opcodes-9bb46c8beaf08ebe1f2f69802a31afa9e31af89e.tar.gz riscv-opcodes-9bb46c8beaf08ebe1f2f69802a31afa9e31af89e.tar.bz2 | |
split dret from rv_system to rv_debug
Because neither priv and unpriv isa mentions dret, and debug is lived in
a standalone spec, move dret out from rv_system, while putting it into
rv_debug
| -rw-r--r-- | rv_debug | 2 | ||||
| -rw-r--r-- | rv_system | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/rv_debug b/rv_debug new file mode 100644 index 0000000..ea1c3ef --- /dev/null +++ b/rv_debug @@ -0,0 +1,2 @@ +# debug +dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 @@ -1,5 +1,4 @@ # SYSTEM mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 -dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 |