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| author | Andrew Waterman <andrew@sifive.com> | 2023-07-10 15:49:12 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-10 15:49:12 -0700 |
| commit | be53d2453ff46e13eba372de208f1c719635e67b (patch) | |
| tree | 8d37408c15977d3bc6fa500fe1cf07903f23ae60 | |
| parent | 3ca60c50f8ea1ea514bcfff58719f670194c1dc8 (diff) | |
| parent | 1d2c34a6423f262f2056e3f2e4119121cf1fd3a1 (diff) | |
| download | riscv-opcodes-be53d2453ff46e13eba372de208f1c719635e67b.zip riscv-opcodes-be53d2453ff46e13eba372de208f1c719635e67b.tar.gz riscv-opcodes-be53d2453ff46e13eba372de208f1c719635e67b.tar.bz2 | |
Merge pull request #178 from rivosinc/smcsrind_sscsrind_csrs
Add Smcsrind/Sscsrind CSRs
| -rw-r--r-- | constants.py | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/constants.py b/constants.py index 8d9352f..98c4b7c 100644 --- a/constants.py +++ b/constants.py @@ -116,6 +116,11 @@ csrs = [ (0x14D, 'stimecmp'), # Sstc (0x150, 'siselect'), (0x151, 'sireg'), + (0x152, 'sireg2'), + (0x153, 'sireg3'), + (0x155, 'sireg4'), + (0x156, 'sireg5'), + (0x157, 'sireg6'), (0x15C, 'stopei'), (0x180, 'satp'), (0x5A8, 'scontext'), @@ -132,6 +137,11 @@ csrs = [ (0x24D, 'vstimecmp'), # Sstc (0x250, 'vsiselect'), (0x251, 'vsireg'), + (0x252, 'vsireg2'), + (0x253, 'vsireg3'), + (0x255, 'vsireg4'), + (0x256, 'vsireg5'), + (0x257, 'vsireg6'), (0x25C, 'vstopei'), (0x280, 'vsatp'), (0x600, 'hstatus'), @@ -207,6 +217,11 @@ csrs = [ (0x34b, 'mtval2'), (0x350, 'miselect'), (0x351, 'mireg'), + (0x352, 'mireg2'), + (0x353, 'mireg3'), + (0x355, 'mireg4'), + (0x356, 'mireg5'), + (0x357, 'mireg6'), (0x35c, 'mtopei'), (0x3a0, 'pmpcfg0'), (0x3a1, 'pmpcfg1'), |