Fixes #2516

Previously,

reg r : UInt<8>, clock with :
  reset => (p, UInt<8>(3))
r is invalid

would compile to:

reg r : UInt<8>, clock
r <= UInt<8>(0)

now it compiles to:

reg r : UInt<8>, clock
wire r_1 : UInt<8>
r_1 is invalid
r <= mux(reset, UInt<8>(3), r_1)

This is consistent with the behavior for a reset with an asynchronous
reset.

(cherry picked from commit 5093da03

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 06ccf51a

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix anno deserialization when class field is not first (#2501)

Update `findTypeHints` to allow for the "class" field in JSON objects to
appear anywhere in the object. This used to rely on the field being the
very first in the object, which is easily violated when reading JSON
data generated externally, since an object's order of fields is
unspecified and can be arbitrarily scrambled.

Fixes #2497.

(cherry picked from commit a2d48a58

)

# Conflicts:
#	src/main/scala/firrtl/annotations/JsonProtocol.scala

* fixup! Fix anno deserialization when class field is not first (#2501)

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Fix faulty MemorySynthInit behavior (#2468)

- Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation.
Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context.

- Refactor MemoryInitSpec for improved results readability

Context:

PR #2166 (commit: 4530152) introduced MemorySynthInit annotation to control whether statement generated with Memory*InitAnnotation (emitted within initial begin block in verilog) should be guarded with ifndef SYNTHESIS or not.
Unfortunately only one configuration (MemoryFileInlineAnnotation) has been tested while the others have been generating incorrect verilog statements (MemoryArrayInitAnnotation and MemoryScalarInitAnnotation).

Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
(cherry picked from commit 475c165c

)

# Conflicts:
#	src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala

* Fix conflict

Co-authored-by: John's Brew <46595442+johnsbrew@users.noreply.github.com>
Co-authored-by: Jean Bruant <jean.bruant@ovhcloud.com>

* Add FileInfo to asyncResetAlwaysBlocks

Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).

RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.

Async always blocks don't provide their only FileInfo, so there are no line numbers.

This commit gives async always block the extra FileInfo to show line numbers for them.

This code:

```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission

class Test extends Module with RequireAsyncReset {
  val io = IO(new Bundle {
    val in = Input(Bool())
    val out = Output(Bool())
  })
  val valid = RegInit(false.B)
  valid := io.in
  io.out := valid
}

object Test extends App {
  new ChiselStage().execute(Array(), Seq(
    ChiselGeneratorAnnotation(() => new Test()),
    CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
  ))
}
```

will generate this Verilog:

```verilog
module Test(
  input   clock,
  input   reset,
  input   io_in,
  output  io_out
);
  reg  valid; // @[Playground.scala 10:22]
  assign io_out = valid; // @[Playground.scala 12:10]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Playground.scala 10:22]
      valid <= 1'h0; // @[Playground.scala 10:22]
    end else begin
      valid <= io_in; // @[Playground.scala 11:9]
    end
  end
endmodule
```

they have correct line numbers (10, 10, 11).

* Add test for async always block line numbers

* Add comment for review

(cherry picked from commit 3e494b5c

)

Co-authored-by: sinofp <sinofp@tuta.io>

8abf3085

 reordered the fields, but it
unintentionally placed a closing brace before the actual end of the
write port type. This moves the brace to the end of the port.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit b2cae19b

)

# Conflicts:
#	spec/spec.pdf

Co-authored-by: Richard Xia <rxia@sifive.com>

The test was leaving the test directory in a dirty state that would fail
on a rerun. Fix the test so that it can be run multiple times in a row.

(cherry picked from commit b8a0ecf1

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Multi protobuf module emission and consumption (#2344)

* Add compiler option (`-p`) to emit individual module protobufs
* Implement multi module combination when reading directory of protobufs

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 0c1ca581

)

* Multi PB backport fixes (#2353)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>

* Fix dshl zero-width shift behavior

Add a special case for dshl handling in the ZeroWidths pass.  If one
expression is shifted by a second, zero-width expression, just return
the first expression.  This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Fix dshl zero-width shift behavior

(cherry picked from commit cc80c631

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize
file emission.

(cherry picked from commit dc2fbad9

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 762f7747

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Correct incorrect type specified for memories in the FIRRTL
specification.  This is important because the memory type determines
what is a legal bundle to try to connect to a memory port.

I based this off of FIRRTL accepting the following circuit:

    circuit MemOrder:
      module MemOrder:
        input r: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip data : UInt<1>}
        input w: {addr : UInt<3>, en : UInt<1>, clk : Clock, data : UInt<1>, mask : UInt<1>}
        input rw: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip rdata : UInt<1>, wmode : UInt<1>, wdata : UInt<1>, wmask : UInt<1>}

        mem memory:
          data-type => UInt<1>
          depth => 8
          reader => r
          writer => w
          readwriter => rw
          read-latency => 1
          write-latency => 1
          read-under-write => undefined

        memory.r <= r
        memory.w <= w
        memory.rw <= rw

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 8abf3085

)

# Conflicts:
#	spec/spec.pdf

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Dedup attribute annos (#2297)

* Add new util "groupByIntoSeq"
* Restore annotation order when dedupping annotations
* Attribute annotations now deduplicate
* Implement doc string anno dedup

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 04210ee3

)

# Conflicts:
#	src/main/scala/firrtl/Utils.scala

* Fix backporting issues for attribute anno deduplication (#2307)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number
of operands.  Verilog emission doesn't support this and will silently
drop all operands after the first.  E.g., "andr(a, b)" would emit as
"&a".  After this commit, "andr(a, b)" will be rejected by checking
passes.

For archaeological purposes, this appears to have been the behavior
dating back to when this was added in d2d3260a

.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit a643cfd3

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

(cherry picked from commit c0479d9a)

Change the FIRRTL spec to disallow a zero-width multiplexer select.
Clarify that the select line can be either one-bit or zero-bit, but will
infer to one-bit.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit ff1cd282

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Fix memory annotation deduplication (#2286)

* Add transform to deduplicate memory annotations
* Add annotation deduplication to Dedup stage
* ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform
* Verilog emitter now throws exception when memory annotations fail to dedup

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 4081d9f4

)

* Fix binary compatibility issues with memory anno dedup transform (#2295)

* Remove unused exception in dedup transform
* Fold Annotation.dedup() into dedup transform for binary compatibility
* ResolvedAnnotationPaths no longer invalidates any transforms
* Use Annotation.copy() instead of constructor in dedup logic

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>

* Add --start-from option (#2273)

Add a new option to the FIRRTL compiler, "--start-from = <form>".  If
used, this will cause the compiler to assume that the input FIRRTL
circuit is already in the specific form.  It will then skip unnecessary
passes given this information.

E.g., if a user requests to run "firrtl -X verilog --start-from low"
then the compiler will only run transforms necessary to get from low
FIRRTL to Verilog.  Transforms necessary for ingesting FIRRTL IR will be
run if needed (checks and type/kind/flow resolution).

To implement this, a CurrentFirrtlStateAnnotation is added.  Advanced
users can use this directly to tell the FIRRTL compiler exactly what
transforms have already been run, including the ability to ignore checks
or type/kind/flow resolution if they so desire.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit c7eaa67d

)

* Waive bincompat issues that don't affect Scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fix VerilogMemDelays use before declaration (#2278)

The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.

(cherry picked from commit 11128d93

)

# Conflicts:
#	src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala

* Fix merge conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add Protocol Buffer emission export

This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.

Fixes #1696.

(cherry picked from commit d708d3f0

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add a compiler/emitter that can target minimal high form.  This will
produce output that only has CHIRRTL constructs removed.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 3ea95e72

)

# Conflicts:
#	src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Replace mem macros renaming (#2243)

* ReplaceMemMacros: add target rename test case

* ReplaceMemMacros: rename references to instances

* fix renaming for deduped mems

* use grouped DummyAnnos to preserve order

* Apply suggestions from code review

Co-authored-by: Jack Koenig <koenig@sifive.com>

* run scalafmt

* flatten targets

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 62fdb87e

)

# Conflicts:
#	src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala

* fix conflicts

* add back old APIs, add new private methods

Co-authored-by: Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
Co-authored-by: Albert Chen <albert.chen@sifive.com>

(cherry picked from commit 117b84a1

)

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fix renaming of local targets in InlineInstances (#2238)

* add more inline renaming test cases

* InlineInstances: fix renaming for local targets

* run scalafmt

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 15309c97

)

# Conflicts:
#	src/main/scala/firrtl/passes/Inline.scala

* Resolve backport conflicts

Co-authored-by: Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit d35248c8

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

* Improve performance of RenameMap in LowerTypes (#2233)

LowerTypes creates a lot of mappings for the RenameMap. The built-in
.distinct of renames becomes a performance program for designs with
deeply nested Aggregates. Because LowerTypes does not create duplicate
renames, it can safely eschew the safety of using .distinct via a
private internal API.

(cherry picked from commit e0844966

)

* Waive bincompat issue that isn't visible from Scala

Co-authored-by: Jack Koenig <koenig@sifive.com>

This function will safely wrap any unserializeable annotations in
UnserializeableAnnotations so that they can be safely serialized to JSON
for logging.

(cherry picked from commit c2d72fd8

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 6db311b3

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 33c0b431

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

Looks like a typo/auto-merge hiccup.

(cherry picked from commit adc2ad9a

)

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>

(cherry picked from commit bf1cf3d2

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:

    circuit Foo :
      module Foo :
        input a: UInt<3>
        output b: UInt<4>
        b <= asUInt(xor(asSInt(a), SInt<4>(0)))

This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.

This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.

(cherry picked from commit e9b2946c

)

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>

Add indent parameter to Serializer.serialize() (backport #2177)

Using Utils.indent() gives deprecation warnings to use Serializer instead. However,
the Serializer class itself doesn't provide a means to manually indent a FirrtlNode
string a certain number of times.

The indent variable, previously hardcoded to 0, is now exposed as a second parameter
for the modified serialize function, and the old serialize function just calls the
modified serialize with indents = 0 for binary compatibility

Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 20890bbd)

This PR adds options for memory initialization inside or outside the
`ifndef SYNTHESIS` block.

(cherry picked from commit d0d3cd4e

)

Co-authored-by: Carlos Eduardo <me@carlosedp.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 9a3dcf76

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

CSESubAccesses was intended to be a simple workaround for a quadratic
performance bug in RemoveAccesses but ended up having tricky corner
cases and was hard to get right. The solution to the RemoveAccesses
bug--quadratic expansion of dynamic indexes of vecs of aggreate
type--turned out to be quite simple and makes CSESubAccesses much less
useful and not worth fixing.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit a41af6f0

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* add --no-constant-propagation to disable constant propagation

* add test

* deprecate DisableFold.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit abeff01f

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>