This is a modified form of #706 to preserve the
bugfix but preserve the [buggy] 1.0.x API that firrtl was not properly
enforcing initialization requirements for submodule inputs

The problem with #706 is that because Firrtl wasn't properly enforcing initialization requirements on submodules, code that used to work no longer does. This alternative version still fixes the incorrect Verilog generation bug but does not enforce the initialization requirement.

This reverts commit 4801d9cb.

Fixes #527 

This resulted in parent modules sometimes being constant proppagated
before a child module. If the child module has a constant driving one of
its outputs, the parent module would thus not see the constant. This
resulted in strange unstable constant propagation behavior where
sometimes constant outputs would not propagate.

Also add test illustrating why this occurs with uses of InstanceGraph

This reverts commit 8ab501e7.

Fixes #708

This reverts commit 8ab501e7.

Bump SBT to 1.0.4 and update plugins
Update Scala versions and sbt commands in .travis.yml
Replace run-main with runMain

Remove wires, replacing them with nodes

Make the check script allow different designs
Add FPU, ICache, and RocketCore to regress and use instead of Rob for CI
equivalence check

This transform replaces all wires with nodes in a legal, flow-forward
order

Move pad to object ConstantPropagation so other transforms can use it

* add graph node classes

* add graph representation usage pass

* remove pass using graph nodes so that firrtl can compile

* move google graph ir nodes to altIR package

Merge branch 'master' into release

Also let Travis know that equivalence checks can take a while