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riscv-isa-manual.git
1437-update-generated-filenames-to-be-more-desciptive
1454-fix-merge-and-release-workflow
1532-lack-of-list-of-figures-tables
Sv57
Svinval
Svnapot
Svpbmt
antora-refactor
aswaterman-patch-1
atomics-wording-v2
bonzini-hpmdelta
cnop
convert2adoc_rvwmo
csr-wip
fix-adoc-IDs
hypervisor
kersten1-patch-3
latex
lrsc
main
misa-ztso
msip
mtime-optional
n-ext
pmp
ratified-priv-v1.11-sans-hypervisor-draft
sail-inclusion-example
sfence-asid
smpmpmt
svkt
tmp
trap
v20240411
virtual-memory
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ztso-ratification
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supervisor.tex
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Author
Files
Lines
2021-10-05
Fix editing error in mtval/stval definition
Andrew Waterman
1
-30
/
+26
2021-09-10
Generalize SSIP to support forthcoming interrupt controllers (#726)
Andrew Waterman
1
-5
/
+2
2021-09-08
Merge pull request #727 from riscv/mseccfg
Andrew Waterman
1
-0
/
+116
2021-09-08
FIOM may be hardwired when satp is hardwired
Andrew Waterman
1
-0
/
+2
2021-09-02
Describe purpose of FIOM mechanism
Andrew Waterman
1
-0
/
+39
2021-09-01
Clarify widths of privileged CSRs (#728)
John Hauser
1
-23
/
+28
2021-08-29
FIOM affects aq/rl, too
Andrew Waterman
1
-0
/
+5
2021-08-29
Add henvcfg/senvcfg CSRs
Andrew Waterman
1
-0
/
+70
2021-08-11
Interrupt conditions are also evaluated on falling edges
Andrew Waterman
1
-1
/
+2
2021-08-11
Generalize interrupt trap condition evaluation conditions (#705)
Andrew Waterman
1
-1
/
+2
2021-08-06
Clarify mepc invalid address conversion
Andrew Waterman
1
-4
/
+6
2021-08-05
Improve description of interrupt traps (#701)
Andrew Waterman
1
-7
/
+14
2021-07-06
Clarify that SFENCE.VMA isn't required for Sbare
Andrew Waterman
1
-0
/
+4
2021-06-26
Add non-normative text about VIPT caches not being exposed
Andrew Waterman
1
-0
/
+9
2021-05-23
Fix hyphenation
Andrew Waterman
1
-1
/
+1
2021-04-23
Minor mstatus and sstatus layout edits. (#642)
Steven Bellock
1
-9
/
+9
2021-04-21
SUM should be hardwired to 0 for cores without paging (#641)
Andrew Waterman
1
-0
/
+2
2020-10-13
Both HWBPs and EBREAKs populate mtval (#601)
Andrew Waterman
1
-2
/
+3
2020-09-28
Clarify that "exception code" is used for both exceptions and interrupts
Andrew Waterman
1
-1
/
+1
2020-09-28
Revert "Add VA canonicalization check to Translation Process section"
Andrew Waterman
1
-15
/
+7
2020-08-25
Change "hardwired to other field" to "read-only field" (#571)
John Hauser
1
-3
/
+4
2020-08-24
Tweak
Andrew Waterman
1
-2
/
+2
2020-08-24
Clarify that ASIDs are (currently) local to a hart
Andrew Waterman
1
-12
/
+11
2020-08-14
Change "reserved for custom" to "designated for custom" (#566)
John Hauser
1
-6
/
+6
2020-08-03
Fix formatting of 2^XLEN
Andrew Waterman
1
-1
/
+1
2020-07-31
Add missing word
Andrew Waterman
1
-1
/
+1
2020-07-31
Clarify that ASID changes are also immediate
Andrew Waterman
1
-0
/
+1
2020-07-31
Clarify that satp.MODE transitions to/from Bare don't require SFENCE.VMA
Andrew Waterman
1
-0
/
+3
2020-07-31
Reserve some satp encodings for custom use
Andrew Waterman
1
-5
/
+11
2020-07-30
Fix Sv48 VALEN typo (#551)
Daniel Lustig
1
-1
/
+1
2020-07-26
Clarify which implicit reads of the translation structures are allowed
Andrew Waterman
1
-1
/
+2
2020-07-25
tweak
Andrew Waterman
1
-1
/
+1
2020-07-25
Add commentary about caching invalid PTEs
Andrew Waterman
1
-0
/
+7
2020-07-17
Remove redundant phrase from access-/page-fault text
Andrew Waterman
1
-1
/
+1
2020-05-18
Clarify that satp.MODE=Bare with satp.LSBs != 0 is unspecified for now
Andrew Waterman
1
-0
/
+3
2020-04-23
Clarify semantics of sfence.vma with rs1 != 0 (#515)
Jonathan Behrens
1
-2
/
+2
2020-04-06
Add commentary about multi-hit/failing to SFENCE.VMA
Andrew Waterman
1
-0
/
+18
2020-03-03
Clarified description of sstatus.
Krste Asanovic
1
-4
/
+5
2020-02-28
Move VALEN check to the top of Translation Process section
Andrew Waterman
1
-2
/
+2
2020-02-28
Add VA canonicalization check to Translation Process section
Andrew Waterman
1
-7
/
+15
2020-02-12
Only describe scounteren in supervisor chapter
Andrew Waterman
1
-0
/
+7
2019-11-11
tweak
Andrew Waterman
1
-2
/
+2
2019-11-10
satp.PPN's WARLness is separate from physical address validity
Andrew Waterman
1
-4
/
+7
2019-11-07
Reserve satp fields when MODE=Bare
Andrew Waterman
1
-2
/
+12
2019-11-06
Convert samepage-commentary blocks to commentary blocks
Andrew Waterman
1
-2
/
+2
2019-10-22
Merge branch 'unspecified' of https://github.com/pdonahue-ventana/riscv-isa-m...
Andrew Waterman
1
-2
/
+2
2019-10-16
clarify that extra PTE bits are reserved for _standard_ use
Andrew Waterman
1
-2
/
+2
2019-10-11
Explicitly remark that SUM/MXR changes don't need an SFENCE.VMA
Andrew Waterman
1
-0
/
+3
2019-10-11
fix formatting
Andrew Waterman
1
-1
/
+1
2019-10-02
Incorporate some of #416 and #418
Andrew Waterman
1
-1
/
+1
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