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AgeCommit message (Expand)AuthorFilesLines
2021-10-05Fix editing error in mtval/stval definitionAndrew Waterman1-30/+26
2021-09-10Generalize SSIP to support forthcoming interrupt controllers (#726)Andrew Waterman1-5/+2
2021-09-08Merge pull request #727 from riscv/mseccfgAndrew Waterman1-0/+116
2021-09-08FIOM may be hardwired when satp is hardwiredAndrew Waterman1-0/+2
2021-09-02Describe purpose of FIOM mechanismAndrew Waterman1-0/+39
2021-09-01Clarify widths of privileged CSRs (#728)John Hauser1-23/+28
2021-08-29FIOM affects aq/rl, tooAndrew Waterman1-0/+5
2021-08-29Add henvcfg/senvcfg CSRsAndrew Waterman1-0/+70
2021-08-11Interrupt conditions are also evaluated on falling edgesAndrew Waterman1-1/+2
2021-08-11Generalize interrupt trap condition evaluation conditions (#705)Andrew Waterman1-1/+2
2021-08-06Clarify mepc invalid address conversionAndrew Waterman1-4/+6
2021-08-05Improve description of interrupt traps (#701)Andrew Waterman1-7/+14
2021-07-06Clarify that SFENCE.VMA isn't required for SbareAndrew Waterman1-0/+4
2021-06-26Add non-normative text about VIPT caches not being exposedAndrew Waterman1-0/+9
2021-05-23Fix hyphenationAndrew Waterman1-1/+1
2021-04-23Minor mstatus and sstatus layout edits. (#642)Steven Bellock1-9/+9
2021-04-21SUM should be hardwired to 0 for cores without paging (#641)Andrew Waterman1-0/+2
2020-10-13Both HWBPs and EBREAKs populate mtval (#601)Andrew Waterman1-2/+3
2020-09-28Clarify that "exception code" is used for both exceptions and interruptsAndrew Waterman1-1/+1
2020-09-28Revert "Add VA canonicalization check to Translation Process section"Andrew Waterman1-15/+7
2020-08-25Change "hardwired to other field" to "read-only field" (#571)John Hauser1-3/+4
2020-08-24TweakAndrew Waterman1-2/+2
2020-08-24Clarify that ASIDs are (currently) local to a hartAndrew Waterman1-12/+11
2020-08-14Change "reserved for custom" to "designated for custom" (#566)John Hauser1-6/+6
2020-08-03Fix formatting of 2^XLENAndrew Waterman1-1/+1
2020-07-31Add missing wordAndrew Waterman1-1/+1
2020-07-31Clarify that ASID changes are also immediateAndrew Waterman1-0/+1
2020-07-31Clarify that satp.MODE transitions to/from Bare don't require SFENCE.VMAAndrew Waterman1-0/+3
2020-07-31Reserve some satp encodings for custom useAndrew Waterman1-5/+11
2020-07-30Fix Sv48 VALEN typo (#551)Daniel Lustig1-1/+1
2020-07-26Clarify which implicit reads of the translation structures are allowedAndrew Waterman1-1/+2
2020-07-25tweakAndrew Waterman1-1/+1
2020-07-25Add commentary about caching invalid PTEsAndrew Waterman1-0/+7
2020-07-17Remove redundant phrase from access-/page-fault textAndrew Waterman1-1/+1
2020-05-18Clarify that satp.MODE=Bare with satp.LSBs != 0 is unspecified for nowAndrew Waterman1-0/+3
2020-04-23Clarify semantics of sfence.vma with rs1 != 0 (#515)Jonathan Behrens1-2/+2
2020-04-06Add commentary about multi-hit/failing to SFENCE.VMAAndrew Waterman1-0/+18
2020-03-03Clarified description of sstatus.Krste Asanovic1-4/+5
2020-02-28Move VALEN check to the top of Translation Process sectionAndrew Waterman1-2/+2
2020-02-28Add VA canonicalization check to Translation Process sectionAndrew Waterman1-7/+15
2020-02-12Only describe scounteren in supervisor chapterAndrew Waterman1-0/+7
2019-11-11tweakAndrew Waterman1-2/+2
2019-11-10satp.PPN's WARLness is separate from physical address validityAndrew Waterman1-4/+7
2019-11-07Reserve satp fields when MODE=BareAndrew Waterman1-2/+12
2019-11-06Convert samepage-commentary blocks to commentary blocksAndrew Waterman1-2/+2
2019-10-22Merge branch 'unspecified' of https://github.com/pdonahue-ventana/riscv-isa-m...Andrew Waterman1-2/+2
2019-10-16clarify that extra PTE bits are reserved for _standard_ useAndrew Waterman1-2/+2
2019-10-11Explicitly remark that SUM/MXR changes don't need an SFENCE.VMAAndrew Waterman1-0/+3
2019-10-11fix formattingAndrew Waterman1-1/+1
2019-10-02Incorporate some of #416 and #418Andrew Waterman1-1/+1
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