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| author | Andrew Waterman <andrew@sifive.com> | 2019-10-22 12:39:55 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-10-22 12:39:55 -0700 |
| commit | d4647022521de88d8bccf59af6de415f8db1388d (patch) | |
| tree | 6dad849851eb74e1536f1922b0dbcbf298e2f6b6 /src/supervisor.tex | |
| parent | 134226764c1f737b50557accb8a5b3d7d9a03808 (diff) | |
| parent | 436c637d506d4843ce7fd23d6430a3bb4907bed9 (diff) | |
| download | riscv-isa-manual-d4647022521de88d8bccf59af6de415f8db1388d.zip riscv-isa-manual-d4647022521de88d8bccf59af6de415f8db1388d.tar.gz riscv-isa-manual-d4647022521de88d8bccf59af6de415f8db1388d.tar.bz2 | |
Merge branch 'unspecified' of https://github.com/pdonahue-ventana/riscv-isa-manual into pdonahue-ventana-unspecified
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 91c36d0..e2c8781 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -896,9 +896,9 @@ Value & Name & Description \\ \label{tab:satp-mode} \end{table} -The number of supervisor physical address bits is implementation-defined; any +The number of supervisor physical address bits is \unspecified; any unimplemented address bits are hardwired to zero in the {\tt satp} register. -The number of ASID bits is also implementation-defined and may be zero. The +The number of ASID bits is also \unspecified\ and may be zero. The number of implemented ASID bits, termed {\mbox {\em ASIDLEN}}, may be determined by writing one to every bit position in the ASID field, then reading back the value in {\tt satp} to see which bit positions in the ASID |