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| author | Andrew Waterman <andrew@sifive.com> | 2021-07-06 22:48:45 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-07-06 22:48:45 -0700 |
| commit | c047eaf46d8dccdea10bf75f12f889cd249b5ad4 (patch) | |
| tree | 7581666cce3e4900d7fd9dc24e8f8b4384467f0b /src/supervisor.tex | |
| parent | 97cf6d395295c106268cdc2f75625717a79be416 (diff) | |
| download | riscv-isa-manual-c047eaf46d8dccdea10bf75f12f889cd249b5ad4.zip riscv-isa-manual-c047eaf46d8dccdea10bf75f12f889cd249b5ad4.tar.gz riscv-isa-manual-c047eaf46d8dccdea10bf75f12f889cd249b5ad4.tar.bz2 | |
Clarify that SFENCE.VMA isn't required for Sbare
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 8b6f1a9..12d305e 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1212,6 +1212,10 @@ Implicitly, this specification does not permit such behavior to be architecturally exposed. \end{commentary} +For implementations that hardwire {\tt satp}.MODE to Bare, attempts to +execute an SFENCE.VMA instruction might raise an illegal instruction +exception. + \subsection{Addressing and Memory Protection} \label{sec:translation} |