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| author | Andrew Waterman <andrew@sifive.com> | 2021-09-10 04:12:41 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-10 04:12:41 -0700 |
| commit | 01069ac96b90bdc330fc4471945639a54e3b3b69 (patch) | |
| tree | a4dca2e6a96e72432af3858ae493674dfbdbed86 /src/supervisor.tex | |
| parent | bac0a5d0a240ec6992f74b79e85d9a55dacb8a80 (diff) | |
| download | riscv-isa-manual-01069ac96b90bdc330fc4471945639a54e3b3b69.zip riscv-isa-manual-01069ac96b90bdc330fc4471945639a54e3b3b69.tar.gz riscv-isa-manual-01069ac96b90bdc330fc4471945639a54e3b3b69.tar.bz2 | |
Generalize SSIP to support forthcoming interrupt controllers (#726)
* Changes to SSIP to support forthcoming interrupt controllers
* Re: SSIP, say more by saying less
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 966b483..83866df 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -475,11 +475,8 @@ the execution environment. Bits {\tt sip}.SSIP and {\tt sie}.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. -If implemented, SSIP is writable in {\tt sip}. -A supervisor-level software interrupt is triggered -on the current hart by writing 1 to SSIP, -while a pending supervisor-level software -interrupt can be cleared by writing 0 to SSIP. +If implemented, SSIP is writable in {\tt sip} and may also be set +to 1 by a platform-specific interrupt controller. \begin{commentary} Interprocessor interrupts are sent to other harts by implementation-specific |