diff options
| author | Andrew Waterman <andrew@sifive.com> | 2020-10-13 14:48:49 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-13 14:48:49 -0700 |
| commit | 51522f98b5cae989c7d161e00b20a08483a2301e (patch) | |
| tree | 142709efeeb67f1442f88192c2cac533cd245d62 /src/supervisor.tex | |
| parent | 298b666f29ef6628d8c1bf8fc5728062703e1f23 (diff) | |
| download | riscv-isa-manual-51522f98b5cae989c7d161e00b20a08483a2301e.zip riscv-isa-manual-51522f98b5cae989c7d161e00b20a08483a2301e.tar.gz riscv-isa-manual-51522f98b5cae989c7d161e00b20a08483a2301e.tar.bz2 | |
Both HWBPs and EBREAKs populate mtval (#601)
This is a normative change, but it is backwards compatible, since writing 0
to mtval remains a legal option.
Resolves #600
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 53f2a3e..3a88c63 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -727,8 +727,9 @@ which exceptions must set {\tt stval} informatively and which may unconditionally set it to zero. -When a hardware breakpoint is triggered, or an instruction, load, or -store address-misaligned, access-fault, or page-fault exception occurs, {\tt stval} +When a breakpoint, +address-misaligned, access-fault, or page-fault exception occurs +on an instruction fetch, load, or store, {\tt stval} is written with the faulting virtual address. On an illegal instruction trap, {\tt stval} may be written with the first XLEN or ILEN bits of the faulting instruction as described below. For other exceptions, {\tt stval} is set to |