riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-01-17	Removing tex files.	Bill Traynor	1	-252/+0
2022-07-26	Clarify that time CSR one-tick constraint is not merely user-level	Andrew Waterman	1	-2/+2
2022-07-26	Restructure commentary sections to move portions close to relevant normative ...	Krste Asanovic	1	-26/+28
2022-07-26	Be consistent in use of "pseudoinstruction".	Krste Asanovic	1	-7/+7
2022-07-26	Remove inconsistencies in the Zihpm description.	Krste Asanovic	1	-9/+19
2022-07-26	Confirm that real-time clock synchronization is a mandate, but also relay in ...	Krste Asanovic	1	-1/+8
2022-07-26	Weaken impossible mandate on clock period, and provide some commentary.	Krste Asanovic	1	-3/+8
2022-07-26	Make clear that non-canonical CSR reads are also legal for counters.	Krste Asanovic	1	-1/+8
2022-07-26	Removed text assuming these were part of a base, and removed explicit referen...	Krste Asanovic	1	-23/+26
2022-07-26	Make chapter heading have name of extensions defined therein.	Krste Asanovic	1	-2/+2
2022-07-26	Clarify definition of [m]time CSR	Andrew Waterman	1	-9/+14
2022-07-26	Define the Zicntr and Zihpm extensions	Andrew Waterman	1	-10/+14
2022-07-26	Improve text in Zicntr section	Andrew Waterman	1	-4/+8
2020-07-20	clarify that high counters are RV32I-only	Andrew Waterman	1	-1/+1
2020-07-19	Add missing word	Andrew Waterman	1	-1/+1
2019-03-07	Tweaks suggested by Bill Huffman	Andrew Waterman	1	-1/+1
2018-11-06	Updated status of counters. Not ready for ratification as there are issues o...	Krste Asanovic	1	-1/+1
2018-08-09	Added description of hardware performance counters.	Krste Asanovic	1	-0/+21
2018-08-07	Broke out actual perf counters into separate chapter.	Krste Asanovic	1	-0/+184