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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2022-06-22 08:35:43 -0700 |
|---|---|---|
| committer | Bill Traynor <btraynor@gmail.com> | 2022-07-26 11:50:16 -0400 |
| commit | f74867c3985e4edafdeb25ec74102efc89cdabd4 (patch) | |
| tree | 52c6cf880063251b88115a6a5691e6cd85cc60ea /src/counters.tex | |
| parent | 8151cadc9bbff52e45bf7352278d36db0c128c48 (diff) | |
| download | riscv-isa-manual-f74867c3985e4edafdeb25ec74102efc89cdabd4.zip riscv-isa-manual-f74867c3985e4edafdeb25ec74102efc89cdabd4.tar.gz riscv-isa-manual-f74867c3985e4edafdeb25ec74102efc89cdabd4.tar.bz2 | |
Be consistent in use of "pseudoinstruction".
Diffstat (limited to 'src/counters.tex')
| -rw-r--r-- | src/counters.tex | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/counters.tex b/src/counters.tex index 71e175b..f1fc1e9 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -52,8 +52,8 @@ to read these CSRs. For base ISAs with XLEN=32, the Zicntr extension enables the three 64-bit read-only user-level counters to be accessed in 32-bit pieces. -The RDCYCLE, RDTIME, and RDINSTRET instructions provide the lower 32 -bits, and the RDCYCLEH, RDTIMEH, and RDINSTRETH instructions provide +The RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions provide the lower 32 +bits, and the RDCYCLEH, RDTIMEH, and RDINSTRETH pseudoinstructions provide the upper 32 bits of the respective counters. \begin{commentary} @@ -64,8 +64,8 @@ example, to impede timing side-channel attacks. The RDCYCLE pseudoinstruction reads the low XLEN bits of the {\tt cycle} CSR which holds a count of the number of clock cycles executed by the processor core on which the hart is running from an -arbitrary start time in the past. RDCYCLEH is only provided when -XLEN=32 and is an instruction that reads bits 63--32 of the same cycle +arbitrary start time in the past. RDCYCLEH is only present when +XLEN=32 and reads bits 63--32 of the same cycle counter. The underlying 64-bit counter should never overflow in practice. The rate at which the cycle counter advances will depend on the implementation and operating environment. The execution @@ -126,7 +126,7 @@ mind. The RDTIME pseudoinstruction reads the low XLEN bits of the {\tt time} CSR, which counts wall-clock real time that has passed from an arbitrary start time in the past. -RDTIMEH is only present with XLEN=32 and reads bits 63--32 of the same +RDTIMEH is only present when XLEN=32 and reads bits 63--32 of the same real-time counter. The underlying 64-bit counter increments by one with each tick of the real-time clock, and, for realistic real-time clock frequencies, should never @@ -145,7 +145,7 @@ return the same result. It is difficult to provide a strict mandate on clock period given the wide variety of possible implementation platforms. The error bound -should be evaluated relative to the requirements of the platform. +should be constrained based on the requirements of the platform. \end{commentary} The real-time clocks of all harts in a single user application @@ -202,7 +202,7 @@ overflowed. For a low-end implementation, the upper 32 bits of each counter can be implemented using software counters incremented by a trap handler triggered by overflow of the lower 32 bits. The sample code described above shows how the full 64-bit width value can be -safely read using the individual 32-bit width instructions. +safely read using the individual 32-bit width pseudoinstructions. In some applications, it is important to be able to read multiple counters at the same instant in time. When run under a multitasking |