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| author | Andrew Waterman <andrew@sifive.com> | 2020-07-20 15:30:00 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-07-20 15:30:00 -0700 |
| commit | 5736b2d3be39b9ae71f5801e1143d87628929c4d (patch) | |
| tree | 9dea403487c81a104df2762abc11fcbd6574b645 /src/counters.tex | |
| parent | a062d17f8eff10909c0653b16cba281cf7a798c8 (diff) | |
| download | riscv-isa-manual-5736b2d3be39b9ae71f5801e1143d87628929c4d.zip riscv-isa-manual-5736b2d3be39b9ae71f5801e1143d87628929c4d.tar.gz riscv-isa-manual-5736b2d3be39b9ae71f5801e1143d87628929c4d.tar.bz2 | |
clarify that high counters are RV32I-only
Diffstat (limited to 'src/counters.tex')
| -rw-r--r-- | src/counters.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/counters.tex b/src/counters.tex index 2139d34..3160a27 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -41,7 +41,7 @@ pieces using CSRRS instructions. In RV64I, the CSR instructions can manipulate 64-bit CSRs. In particular, the RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of the {\tt cycle}, {\tt time}, and {\tt instret} counters. Hence, the RDCYCLEH, RDTIMEH, -and RDINSTRETH instructions are not required in RV64I. +and RDINSTRETH instructions are RV32I-only. \begin{commentary} Some execution environments might prohibit access to counters to |