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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-07 13:42:32 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-07 13:42:32 -0800 |
| commit | f3663bddccd838842154aed6db44d93dfc19d009 (patch) | |
| tree | 041400ca5b4dd0c852e50be0069d7eab8ca17dcd /src/counters.tex | |
| parent | 47ca7ce69c566b4c59923d87ce7c1875f4ff4b80 (diff) | |
| download | riscv-isa-manual-f3663bddccd838842154aed6db44d93dfc19d009.zip riscv-isa-manual-f3663bddccd838842154aed6db44d93dfc19d009.tar.gz riscv-isa-manual-f3663bddccd838842154aed6db44d93dfc19d009.tar.bz2 | |
Tweaks suggested by Bill Huffman
Diffstat (limited to 'src/counters.tex')
| -rw-r--r-- | src/counters.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/counters.tex b/src/counters.tex index 1700f15..a22a541 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -137,7 +137,7 @@ instruction counter. The underlying 64-bit counter should never overflow in practice. The following code sequence will read a valid 64-bit cycle counter value into -{\tt x3}:{\tt x2}, even if the counter overflows between reading its upper +{\tt x3}:{\tt x2}, even if the counter overflows its lower half between reading its upper and lower halves. \begin{figure}[h!] |