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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2022-06-21 22:40:29 -0700 |
|---|---|---|
| committer | Bill Traynor <btraynor@gmail.com> | 2022-07-26 11:50:16 -0400 |
| commit | 4cee5776370711097e27fa00b6ecd3e82f448dc6 (patch) | |
| tree | 5f28a192abe50c3d034b72f77853401a6c01891f /src/counters.tex | |
| parent | 82ab76b8fea8384dfb02d3d9b2922bb60bce5f67 (diff) | |
| download | riscv-isa-manual-4cee5776370711097e27fa00b6ecd3e82f448dc6.zip riscv-isa-manual-4cee5776370711097e27fa00b6ecd3e82f448dc6.tar.gz riscv-isa-manual-4cee5776370711097e27fa00b6ecd3e82f448dc6.tar.bz2 | |
Make chapter heading have name of extensions defined therein.
Diffstat (limited to 'src/counters.tex')
| -rw-r--r-- | src/counters.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/counters.tex b/src/counters.tex index 76fbf9b..19360ed 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -1,7 +1,7 @@ -\chapter{Counters} +\chapter{``Zicntr'' and ``Zihpm'' Counters} \label{counters} -RISC-V ISAs provide a set of up to 32$\times$64-bit performance counters and +RISC-V ISAs provide a set of up to thirty-two 64-bit performance counters and timers that are accessible via unprivileged XLEN-bit read-only CSR registers {\tt 0xC00}--{\tt 0xC1F} (with the upper 32 bits accessed via CSR registers {\tt 0xC80}--{\tt 0xC9F} on RV32). |