| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2023-01-17 | Removing tex files. | Bill Traynor | 1 | -252/+0 | |
| Beginning to remove tex files from asciidoc branch. | |||||
| 2022-07-26 | Clarify that time CSR one-tick constraint is not merely user-level | Andrew Waterman | 1 | -2/+2 | |
| It's effectively an unprivileged constraint, not just user-level. | |||||
| 2022-07-26 | Restructure commentary sections to move portions close to relevant normative ↵ | Krste Asanovic | 1 | -26/+28 | |
| text. | |||||
| 2022-07-26 | Be consistent in use of "pseudoinstruction". | Krste Asanovic | 1 | -7/+7 | |
| 2022-07-26 | Remove inconsistencies in the Zihpm description. | Krste Asanovic | 1 | -9/+19 | |
| Add clarifications on possible exceptions. Move description of more privileged CSRs that control events to non-normative text as alternative user-mode execution environments don't have these. | |||||
| 2022-07-26 | Confirm that real-time clock synchronization is a mandate, but also relay in ↵ | Krste Asanovic | 1 | -1/+8 | |
| commentary that this is only an "as if" architectural requirement. | |||||
| 2022-07-26 | Weaken impossible mandate on clock period, and provide some commentary. | Krste Asanovic | 1 | -3/+8 | |
| 2022-07-26 | Make clear that non-canonical CSR reads are also legal for counters. | Krste Asanovic | 1 | -1/+8 | |
| 2022-07-26 | Removed text assuming these were part of a base, and removed explicit ↵ | Krste Asanovic | 1 | -23/+26 | |
| reference to particular base ISAs. | |||||
| 2022-07-26 | Make chapter heading have name of extensions defined therein. | Krste Asanovic | 1 | -2/+2 | |
| 2022-07-26 | Clarify definition of [m]time CSR | Andrew Waterman | 1 | -9/+14 | |
| This commit results in no normative change but is meant to clear up confusion expressed in the following thread: https://lists.riscv.org/g/tech-unixplatformspec/message/1494 In particular, each increment of the time CSR corresponds to exactly one RTC tick. | |||||
| 2022-07-26 | Define the Zicntr and Zihpm extensions | Andrew Waterman | 1 | -10/+14 | |
| These extensions comprise the already-ratified counters. | |||||
| 2022-07-26 | Improve text in Zicntr section | Andrew Waterman | 1 | -4/+8 | |
| 2020-07-20 | clarify that high counters are RV32I-only | Andrew Waterman | 1 | -1/+1 | |
| 2020-07-19 | Add missing word | Andrew Waterman | 1 | -1/+1 | |
| The RDTIMEH and RDINSTRETH are described as RV32I-only instructions, but RDCYCLEH was mistakenly described as RV32I rather than RV32I-only. | |||||
| 2019-03-07 | Tweaks suggested by Bill Huffman | Andrew Waterman | 1 | -1/+1 | |
| 2018-11-06 | Updated status of counters. Not ready for ratification as there are issues ↵ | Krste Asanovic | 1 | -1/+1 | |
| outstanding. | |||||
| 2018-08-09 | Added description of hardware performance counters. | Krste Asanovic | 1 | -0/+21 | |
| 2018-08-07 | Broke out actual perf counters into separate chapter. | Krste Asanovic | 1 | -0/+184 | |
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index : riscv-isa-manual.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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