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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-11-06 19:15:49 -0800 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-11-06 19:15:49 -0800 |
| commit | 5e08f27d7124f147b703b2a29dbbc8a88132f305 (patch) | |
| tree | f38f848bfdd83bce757324ffc9c5b5a0fb303e23 /src/counters.tex | |
| parent | b9cb91436f409fd16988f27de86c29d2eb232355 (diff) | |
| download | riscv-isa-manual-5e08f27d7124f147b703b2a29dbbc8a88132f305.zip riscv-isa-manual-5e08f27d7124f147b703b2a29dbbc8a88132f305.tar.gz riscv-isa-manual-5e08f27d7124f147b703b2a29dbbc8a88132f305.tar.bz2 | |
Updated status of counters. Not ready for ratification as there are issues outstanding.
Diffstat (limited to 'src/counters.tex')
| -rw-r--r-- | src/counters.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/counters.tex b/src/counters.tex index 65c95b7..1700f15 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -133,7 +133,7 @@ The RDINSTRET pseudoinstruction reads the low XLEN bits of the {\tt instret} CSR, which counts the number of instructions retired by this hart from some arbitrary start point in the past. RDINSTRETH is an RV32I-only instruction that reads bits 63--32 of the same -instruction counter. The underlying 64-bit counter that should never +instruction counter. The underlying 64-bit counter should never overflow in practice. The following code sequence will read a valid 64-bit cycle counter value into |