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6 hoursFound and tagged WARL/WLRL with Copilot AI assistance. (#2653)HEADriscv-isa-release-464b564-2026-02-11mainJames Ball1-1/+1
3 daysMerge branch 'main' into 20260120v20260120Bill Traynor15-79/+183
4 days[Norm Tags] Updated Norm Rules for B-extension (#2628)riscv-isa-release-76d7a02-2026-02-06Umer Shahid1-23/+133
4 days[Norm Tags] Resolved Jamesball reported issues (#2652)Umer Shahid6-38/+37
5 daysremove spurious smstaten text from JVT (#2637)riscv-isa-release-2a857eb-2026-02-05Tariq Kurd1-5/+0
5 daysFix some typos (#2656)riscv-isa-release-57aceb6-2026-02-05Andrew Waterman8-12/+12
5 daysMention where `mvip` is defined. (#2649)riscv-isa-release-945b6a8-2026-02-05Prashanth Mundkur1-1/+1
8 daysAdd new unpriv prefaceAndrew Waterman1-0/+69
8 daysFix unpriv prefaceAndrew Waterman1-8/+2
8 daysFix: Rename 'Hypervisor-Level' to 'HS-Level' in Figure 29 (#2634)riscv-isa-release-f30292b-2026-02-03Divyam Shankhdhar1-2/+2
8 days[Norm Tags] Cfi patch, merged PR #2627 & PR #2626 (#2636)Umer Shahid1-7/+7
11 daysMerge branch 'main' into pr/crypto-typoBill Traynor1-1/+1
11 daysClarify CSR privilege encoding convention for hypervisor CSRs. (#2631)riscv-isa-release-472227f-2026-01-30Prashanth Mundkur1-1/+1
11 daysFix typo zvkhnb -> zvknhb.Craig Topper1-2/+2
12 daysAdded Normative Rules for scalar crypto extension (#2579)riscv-isa-release-f2dd81c-2026-01-29Umer Shahid1-0/+4
12 days[Norm Tags] Normative Rules for smcdeleg extension (#2571)Umer Shahid1-24/+17
12 days[Norm Tags] Normative Rules for smstateen extension (#2608)riscv-isa-release-4463f55-2026-01-29Umer Shahid1-56/+66
12 daysAdded Norm Rules for indirect-csr-access extension (#2606)Umer Shahid1-22/+33
12 days[Norm Tags] Normative Rules for Sscofpmf extension (#2605)Umer Shahid1-14/+17
12 daysAdded Normative Rules for Zawrs Extension (#2604)Umer Shahid1-12/+12
12 daysAdded Normative Rules for Zabha Extension (#2581)Umer Shahid1-5/+5
12 days[Norm Tags] Normative Rules for Zacas Extension (#2580)Umer Shahid1-22/+22
12 daysAdded Normative rules for supervisor chapter (#2621)Umer Shahid1-181/+245
2026-01-26Merge branch 'main' into 42-AMO-newUmer Shahid6-449/+479
2026-01-25Add note that Svnapot is usable in G-stage PTEs (#2599)riscv-isa-release-3c31d27-2026-01-25Andrew Waterman1-0/+3
2026-01-23Improve manual formating of Chapter CSR in Privilige Manual (#2593)riscv-isa-release-10306e5-2026-01-23Xu, Zefan1-36/+37
2026-01-23Minor changes in smepmp.adoc and rv32.adoc to resolve referencing issues, upd...umershahidengr2-4/+4
2026-01-23Merge branch 'riscv:main' into machine-modeUmer Shahid1-1/+1
2026-01-23Merged all machine mode norm rulesumershahidengr1-408/+434
2026-01-23Clarify that Zicfiss depends on the Zaamo extension.Prashanth Mundkur1-1/+1
2026-01-22Cleaned up AMO Normative tags, and reviewed itumershahidengr1-64/+64
2026-01-20Fixed spelling of mcountinhibit in normative rules, added branch and jump tag...riscv-isa-release-6ad05e3-2026-01-21David Harris2-9/+12
2026-01-16Make mseccfgh presence explicit (#2575)riscv-isa-release-3b63260-2026-01-17Andrew Waterman1-1/+2
2026-01-16Clarify which vstart values are reserved for whole register instructions (#2572)riscv-isa-release-57ff123-2026-01-17Andrew Waterman1-4/+10
2026-01-15Fix 'Reserved for counter-overflow interrupt' text (#2567)riscv-isa-release-4ccf51d-2026-01-16Tim Hutt1-1/+1
2026-01-14Clarify counter/timer behavior in critical-error state (#2568)riscv-isa-release-3d19e7c-2026-01-15Ved Shanbhogue1-1/+2
2026-01-05Clarify when mseccfg exists (#2550)riscv-isa-release-fd45485-2026-01-06Jordan Carlin2-3/+4
2026-01-05Adding ~2000 normative rules from CSC to main repo (#2518)riscv-isa-release-791314b-2026-01-05james-ball-qualcomm36-2017/+2555
2026-01-04Update misaligned atomicity granule summary in A chapter to match Machine cha...riscv-isa-release-103fee6-2026-01-05Jordan Carlin1-1/+1
2026-01-02Fix Zbkb-sc, Zbkc-sc, and Zbkx-sc references (#2548)riscv-isa-release-a4f272e-2026-01-02David Harris1-3/+3
2025-12-24Clarify ill-configured counters (#2539)riscv-isa-release-bd49f88-2025-12-25Ved Shanbhogue1-3/+5
2025-12-24Fix bitmanip integration (#2538)riscv-isa-release-117c442-2025-12-25Ved Shanbhogue3-583/+239
2025-12-24fix bit-width for RoundKeyB in vaeskf2.vi Sail pseudocode (#2487)riscv-isa-release-ad48ae8-2025-12-24riscv-isa-release-851c681-2025-12-24GH41691-1/+1
2025-12-23Adding Zalasr to the main spec (#2091)Brendan Sweeney3-0/+137
2025-12-23Fix a typo in operation of vsha2c[hl].vv instruction (#2536)riscv-isa-release-7f956f7-2025-12-23Xu, Zefan1-1/+1
2025-12-22Fix incorrect non-normative text in memory-model appendix (#2535)riscv-isa-release-1d89943-2025-12-23Andrew Waterman1-5/+4
2025-12-22remove redundant parentheses in vghsh.vv Sail pseudocode (#2530)riscv-isa-release-5c823ad-2025-12-23GH41691-1/+1
2025-12-20[#2386] unifying carry-less spelling in vector crypto chapter (#2527)riscv-isa-release-59e4363-2025-12-20Nicolas Brunie1-12/+12
2025-12-20Synchronize RV32 and RV64 HINT tables wrt. FENCE (#2526)riscv-isa-release-2efad6f-2025-12-20Andrew Waterman2-37/+37
2025-12-19Explicitly clarify that WFI in U-mode is unaffected by mstatus.TW (#2517)riscv-isa-release-936aa76-2025-12-20Ved Shanbhogue1-4/+2
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