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10 daysIf ABI not already passed in then parameterize it based on selected XLEN (#566)HEADmasterTommy Murphy1-1/+8
2024-05-31Merge pull request #557 from en-sc/en-sc/manual-hwbpEvgeniy Naydanov1-3/+19
debug: fix HwbpManual test
2024-05-30Support more basic testing of Zca instructionsAndrew Waterman1-13/+13
Continuation of fee361fd89edd4ac031a570affde16f4f84414e9
2024-05-30Support basic testing of more Zca instructionsAndrew Waterman1-76/+76
By using Zca-friendly registers, we can reuse the existing tests to get quick-and-dirty coverage of Zca, when the assembler is told to use Zca. (This doesn't break non-Zca targets.)
2024-05-23debug: fix HwbpManual testEvgeniy Naydanov1-3/+19
HwbpManual test was broken: * Value read back from `tselect` was compared with `tdata1` value. https://github.com/riscv-software-src/riscv-tests/blob/408e461da11e0b298c4b69e587729532787212f5/debug/gdbserver.py#L701-L703 This resulted in the test being reported as not supported, after all the triggers were checked. * `tdata1.type` field was not set to `mcontrol`. * `tselect` value used to be changed by `handle_reset` and not restored. https://github.com/riscv-software-src/riscv-tests/blob/408e461da11e0b298c4b69e587729532787212f5/debug/programs/entry.S#L79-L84 * Manual breakpoint used to be left behind. Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-05-16Merge pull request #555 from aap-sc/aap-sc/sporadic_faulure_fixEvgeniy Naydanov1-1/+6
debug: workaround for sporadic failures of some tests due to unexpected data present in pexpect match
2024-05-16Merge pull request #556 from aap-sc/aap-sc/sampling_sporadic_failureEvgeniy Naydanov1-0/+1
debug: fix sporadic failures of memory sampling tests
2024-05-15debug: fix sporadic failures of memory sampling testsParshintsev Anatoly1-0/+1
Memory sampling tests fail sporadically for spike targets. A typical failure looks as follows (ROI from test log): ``` ---------------------------------[ Message ]---------------------------------- 139670831 not less than 124104544 --------------------------------[ Traceback ]--------------------------------- ... SECTION IS SKIPPED FOR READABILITY ... raise TestFailed(f"{a!r} not less than {b!r}", comment) testlib.TestFailed ``` Few observations: - 139670831 is 0x0853352f in hex, while 124104544 is 0x0765af60 - Now, the assert which is failing corresponds to the following expression: ``` assertLess(value, previous_value + tolerance) ``` - tolerance is `0x500000`. (124104544 - 0x500000) is 0x0715af60 If we look at the sampling output for such failing test, we'll see: ``` ... 0x1212340c5c: 0x0715af60 timestamp after: 878087500 timestamp before: 878088133 0x1212340c5c: 0x0853352f ... ``` The log above demonstrates the reason for the failure. Since memory sampling occures every poll (which by default happens approximately every 100ms) a value of the counter may exceed the threshold if the time between subsequent polls is increased (for whatever reason). In my opinion the failing assert can be safely removed, since the checks it perform are quite brittle and cannot be generalized. The assert violation is affected by CPU performance and sporadic delays between polls. For now, instead of assert removal we just avoid checks in-between memory sample bursts. This way we still can be certain that memory samples are frequent enough and hopefully this will avoid sporadic failures.
2024-05-14debug: workaround for sporadic failures of some tests due to unexpected data ↵Parshintsev Anatoly1-1/+6
present in pexpect match Problem was observed on UnavailableMultiTest - this test was sporadically failing. When the failure was observed the log of the failing test looked as follows: ``` File "/whatever/RISCVTests/debug/testlib.py", line 504, in <genexpr> if all(targets[hart.id]["State"] == "running" for hart in harts): ~~~~~~~~~~~~~~~~^^^^^^^^^ KeyError: 'State' ``` Adding this modification to testlib.py ``` --- a/debug/testlib.py +++ b/debug/testlib.py @@ -498,6 +498,10 @@ class Openocd: for line in lines[2:]: if line.strip(): data.append(dict(zip(headers, line.split()[1:]))) + str_data = str(data) + sys.stdout.flush() + sys.stdout.write(f"parsed targets:\n{result}\n===\n{str_data}\n---\n") + sys.stdout.flush() return data ``` Allowed me to root cause the issue. Namely we have the following situation: ``` parsed targets: Exception ignored in: <function _TemporaryFileCloser.__del__ at 0x7f2dee64d1c0> Traceback (most recent call last): File "/usr/local/lib/python3.11/tempfile.py", line 450, in __del__ self.close() File "/usr/local/lib/python3.11/tempfile.py", line 446, in close unlink(self.name) FileNotFoundError: [Errno 2] No such file or directory: '/tmp/gdb@38873-8s6ud03x.log' ... TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0 riscv.cpu0 riscv little riscv.cpu running 1* riscv.cpu1 riscv little riscv.cpu running === [{'Exception': '"/usr/local/lib/python3.11/tempfile.py",', 'ignored': 'line', 'in:': '450,', ... ``` The only reasonable (to me) explanation for the observed behavior is below. Here is how we connect to TCL-RPC server: ``` self.openocd_cli = pexpect.spawn(f"nc localhost {self.tclrpc_port}") tty.setraw(self.openocd_cli.child_fd) ``` Later we request target list by issuing "targets" command: ``` self.command("targets") ``` Internally, pexpect.spawn implemented as follows: - we fork the process - set up pty and then call execve - all these steps are written in python "Exception ignored" messages are result of exceptions thrown from finalizers of NamedTemporaryFile objects. When exception is thrown from the finalizer - python unconditionally prints a "warning" to stderr. It seems that these messages are polluting our output from "nc" since python GC can be invoked before the execve syscall. The workaround is just to make sure that execve was executed before we rely on the format of command output. To have such a guarantee we just issue a dummy "echo" command and check that we have a proper reply in the output stream. While this explanation looks convincing, the behavior above still looks strange, given that we have https://bugs.python.org/issue14548 which was resolved long ago. However, the proposed workaround fixes the issue.
2024-05-13Merge pull request #491 from en-sc/en-sc/warning-repeat-readAnatoly Parshintsev1-4/+0
Remove old warning check in RepeatReadTest
2024-05-09Merge pull request #549 from leesum1/trigger-fixAnatoly Parshintsev1-1/+2
debug: Fix nonexistent trigger registers trap handle in entry.S
2024-05-04Merge pull request #544 from lz-bro/debug-test-ubuntu-20.04Anatoly Parshintsev1-1/+1
Use Ubuntu 20.04 for debug tests
2024-05-04Merge pull request #554 from MarekVCodasip/exclusion-fixAnatoly Parshintsev1-1/+5
debug: Fix loading of empty exclude lists with comments
2024-05-02debug: Fix loading of empty exclude lists with commentsMarek Vrbka1-1/+5
This patch fixes the case when we are using an empty exception list (for example just a YAML file with comments but without any test items to skip).
2024-05-01[debug tests] increase remotetimeout for all spike-based targets (#553)Anatoly Parshintsev8-10/+8
Spike simulator is very demanding to CPU resources. This causes debug tests to sporadically fail on slower machines. Increasing of gdb's `remotetimeout` should get rid of such failures, unless we run the testsuite on a potato. The only downside is that if OpenOCD is broken, tests can run longer. However, I think this is the sacrifice we can make, since execution time is not affected if everything works as expected.
2024-04-17debug: Fix nonexistent trigger registers trap handle in entry.Szilong1-1/+2
2024-04-02Merge pull request #534 from lz-bro/fix_triggerDmodeAnatoly Parshintsev1-1/+1
Check the mcontrol triggers, no other triggers.
2024-03-19ma_addr: permit access faults in lieu of misaligned exceptionsAndrew Waterman1-1/+6
2024-03-05Fix CI debug test using ubuntu-20.04梁镇1-1/+1
Signed-off-by: 梁镇 <zhen.liang@spacemit.com> Change-Id: I4657a0417b79d515655f6ad4a5ba4465ca58061f
2024-03-02Merge pull request #533 from lz-bro/fix_icountAnatoly Parshintsev1-0/+1
Clear breakpoints so that gdb will not single step
2024-03-01Merge pull request #531 from aap-sc/aap-sc/improvementsEvgeniy Naydanov2-3/+33
improvements to debug tests infrastructure to help with triaging process
2024-02-29Merge pull request #532 from lz-bro/mb_translateAndrew Waterman1-0/+1
Add virtual memory synchronization after completing the page tables
2024-02-29Merge pull request #526 from lz-bro/fix_TranslateTestAndrew Waterman1-0/+4
Restore $stap and $mstatus after test translate
2024-02-18Fix breakpoint testAndrew Waterman1-0/+3
See https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214
2024-02-18Merge pull request #539 from rogerchang23424/bitmanipAndrew Waterman84-2/+4910
Add bitmanip test cases
2024-02-19Add zbs test casesRoger Chang19-2/+773
Signed-off-by: Roger Chang <rogerycchang@google.com>
2024-02-19Add zbc test casesRoger Chang9-2/+520
Signed-off-by: Roger Chang <rogerycchang@google.com>
2024-02-19Add zbb test casesRoger Chang45-2/+2665
Signed-off-by: Roger Chang <rogerycchang@google.com>
2024-02-19Add zba test casesRoger Chang14-2/+958
Signed-off-by: Roger Chang <rogerycchang@google.com>
2024-02-04Check the mcontrol triggers, no other triggers.liangzhen1-1/+1
Signed-off-by: liangzhen <zhen.liang@spacemit.com> Change-Id: Iac914aef8080411e6acd9039c4bdfa728533103c
2024-02-02Merge pull request #536 from eiji-y/check_svnapotAndrew Waterman1-0/+11
If Svnapot is not implemented, skip the test.
2024-02-03If Svnapot is not implemented, skip the test.Eiji Yoshiya1-0/+11
If Svnapot is not implemented, a page fault will occur when accessing a page with napot specified. In this case, let the test pass.
2024-02-02Clear breakpoints so that gdb will not single stepliangzhen1-0/+1
Signed-off-by: liangzhen <zhen.liang@spacemit.com> Change-Id: I7a4a24972cfa2ddc307a5f06fe3fd5380794719f
2024-02-02Add virtual memory synchronization after completing the page tablesliangzhen1-0/+1
Signed-off-by: liangzhen <zhen.liang@spacemit.com> Change-Id: Ida1490338d204541c5c7f143aec3b8d79d83d7f4
2024-02-01[debug tests] fix setting of remotetimeoutParshintsev Anatoly1-1/+0
fixes setting of `remotetimeout`. It was silently overwritten by default values from platform definition even if user specified one.
2024-02-01[debug tests] add option to log GDB remote serial protocolParshintsev Anatoly1-2/+21
introduce a new option to log communications over GDB remote serial protocol which is helpful for debugging some tests.
2024-02-01[debug tests] print selected seed for PRNGParshintsev Anatoly2-0/+12
Previously the seed was not printed and this created problems with reproduction of the issues. It's still not an ideal - meaning interactions between spike/gdb/openocd are inherently non-determistic (since time is involved), but at least we should get the same sources for the same seed now.
2024-01-29Merge pull request #528 from powdr-labs/masterAndrew Waterman1-1/+1
Uses appropriate addi instruction in lrsc test.
2024-01-29Uses appropriate addi instruction in lrsc test.Lucas Clemente Vella1-1/+1
2024-01-23Disable mmu after test translateliangzhen1-0/+4
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-11-10Merge pull request #522 from aap-sc/aap-sc/unavailable_fixupTim Newsome1-29/+38
debug: use TCL-RPC to fetch results of OpenOCD commands instead of parsing log file
2023-11-09debug: use TCL-RPC to fetch results of OpenOCD commands instead of parsing ↵Parshintsev Anatoly1-29/+38
log file Quick and dirty fix for https://github.com/riscv-software-src/riscv-tests/issues/520
2023-10-25Merge pull request #519 from lz-bro/fix_icountTim Newsome2-2/+9
Support limits_icount_to_one in IcountTest
2023-10-24Support instruction count limit in IcountTestliangzhen2-2/+9
This is taking into account that the hardware limits count to 1. Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-17Merge pull request #513 from lz-bro/nonexist_csrTim Newsome2-4/+8
Make the non-existent csr configurable
2023-10-17Merge pull request #514 from lz-bro/timer_configurableTim Newsome4-7/+17
Make CLINT address configurable
2023-10-17Merge pull request #515 from riscv-software-src/unavailable_halted2Tim Newsome1-0/+61
debug: Add UnavailableHaltedTest
2023-10-17Make the non-existent csr configurableliangzhen2-4/+8
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-16Make CLINT address configurableliangzhen4-7/+17
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-13debug: Add UnavailableHaltedTestTim Newsome1-0/+61
Test behavior when a hart becomes unavailable while halted.