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| author | Roger Chang <rogerycchang@google.com> | 2024-02-19 11:29:33 +0800 |
|---|---|---|
| committer | Roger Chang <rogerycchang@google.com> | 2024-02-19 11:29:33 +0800 |
| commit | a3498c6d2f770af95964a0a7ba46f285cecd1eb3 (patch) | |
| tree | 4d216b0e0c5f0989e052da725464c89d72ee873e | |
| parent | 45476161d6c42c321458027b70fc03a97f6e4ad7 (diff) | |
| download | riscv-tests-a3498c6d2f770af95964a0a7ba46f285cecd1eb3.zip riscv-tests-a3498c6d2f770af95964a0a7ba46f285cecd1eb3.tar.gz riscv-tests-a3498c6d2f770af95964a0a7ba46f285cecd1eb3.tar.bz2 | |
Add zbb test cases
Signed-off-by: Roger Chang <rogerycchang@google.com>
45 files changed, 2665 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index ffd82ff..28ae6a6 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -15,6 +15,7 @@ include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64uzfh/Makefrag include $(src_dir)/rv64uzba/Makefrag +include $(src_dir)/rv64uzbb/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag @@ -28,6 +29,7 @@ include $(src_dir)/rv32uf/Makefrag include $(src_dir)/rv32ud/Makefrag include $(src_dir)/rv32uzfh/Makefrag include $(src_dir)/rv32uzba/Makefrag +include $(src_dir)/rv32uzbb/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -52,10 +54,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb --misaligned $< 2> $@ define compile_template @@ -89,6 +91,7 @@ $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) $(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) @@ -100,6 +103,7 @@ $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) $(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) +$(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) diff --git a/isa/rv32uzbb/Makefrag b/isa/rv32uzbb/Makefrag new file mode 100644 index 0000000..752f8d0 --- /dev/null +++ b/isa/rv32uzbb/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv32uzbb tests +#----------------------------------------------------------------------- + +rv32uzbb_sc_tests = \ + andn \ + clz \ + cpop \ + ctz \ + max maxu \ + min minu \ + orc_b \ + orn \ + rev8 \ + rol \ + ror \ + rori \ + sext_b sext_h \ + xnor \ + zext_h \ + +rv32uzbb_p_tests = $(addprefix rv32uzbb-p-, $(rv32uzbb_sc_tests)) +rv32uzbb_v_tests = $(addprefix rv32uzbb-v-, $(rv32uzbb_sc_tests)) +rv32uzbb_ps_tests = $(addprefix rv32uzbb-ps-, $(rv32uzbb_sc_tests)) + +spike_tests += $(rv32uzbb_p_tests) $(rv32uzbb_v_tests) diff --git a/isa/rv32uzbb/andn.S b/isa/rv32uzbb/andn.S new file mode 100644 index 0000000..f54aa1a --- /dev/null +++ b/isa/rv32uzbb/andn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/andn.S" diff --git a/isa/rv32uzbb/clz.S b/isa/rv32uzbb/clz.S new file mode 100644 index 0000000..4b349ad --- /dev/null +++ b/isa/rv32uzbb/clz.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clz.S +#----------------------------------------------------------------------------- +# +# Test clz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clz, 32, 0x00000000); + TEST_R_OP( 3, clz, 31, 0x00000001); + TEST_R_OP( 4, clz, 30, 0x00000003); + + TEST_R_OP( 5, clz, 0, 0xffff8000 ); + TEST_R_OP( 6, clz, 8, 0x00800000 ); + TEST_R_OP( 7, clz, 0, 0xffff8000 ); + + TEST_R_OP( 8, clz, 17, 0x00007fff); + TEST_R_OP( 9, clz, 1, 0x7fffffff); + TEST_R_OP( 10, clz, 13, 0x0007ffff ); + + TEST_R_OP( 11, clz, 0, 0x80000000); + TEST_R_OP( 12, clz, 3, 0x121f5000); + + TEST_R_OP( 13, clz, 5, 0x04000000); + TEST_R_OP( 14, clz, 28, 0x0000000e); + TEST_R_OP( 15, clz, 2, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clz, 28, 13); + TEST_R_SRC1_EQ_DEST( 17, clz, 28, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clz, 28, 13); + TEST_R_DEST_BYPASS( 29, 1, clz, 27, 19); + TEST_R_DEST_BYPASS( 20, 2, clz, 26, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + + TEST_R_OP( 21, clz, 5, 0x070f8000 ); + TEST_R_OP( 22, clz, 4, 0x08008000 ); + TEST_R_OP( 23, clz, 3, 0x18008000 ); + + TEST_R_OP( 24, clz, 17, 0x00007fff); + TEST_R_OP( 25, clz, 1, 0x7fffffff); + TEST_R_OP( 26, clz, 13, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/cpop.S b/isa/rv32uzbb/cpop.S new file mode 100644 index 0000000..4d97758 --- /dev/null +++ b/isa/rv32uzbb/cpop.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpop.S +#----------------------------------------------------------------------------- +# +# Test cpop instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpop, 0, 0x00000000); + TEST_R_OP( 3, cpop, 1, 0x00000001); + TEST_R_OP( 4, cpop, 2, 0x00000003); + + TEST_R_OP( 5, cpop, 17, 0xffff8000 ); + TEST_R_OP( 6, cpop, 1, 0x00800000 ); + TEST_R_OP( 7, cpop, 18, 0xffff6000 ); + + TEST_R_OP( 8, cpop, 15, 0x00007fff); + TEST_R_OP( 9, cpop, 31, 0x7fffffff); + TEST_R_OP( 10, cpop, 19, 0x0007ffff ); + + TEST_R_OP( 11, cpop, 1, 0x80000000); + TEST_R_OP( 12, cpop, 9, 0x121f5000); + + TEST_R_OP( 13, cpop, 0, 0x00000000); + TEST_R_OP( 14, cpop, 3, 0x0000000e); + TEST_R_OP( 15, cpop, 7, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpop, 8, 0x007f8000 ); + TEST_R_OP( 22, cpop, 2, 0x00808000 ); + TEST_R_OP( 23, cpop, 3, 0x01808000 ); + + TEST_R_OP( 24, cpop, 17, 0x30007fff); + TEST_R_OP( 25, cpop, 30, 0x77ffffff); + TEST_R_OP( 26, cpop, 19, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/ctz.S b/isa/rv32uzbb/ctz.S new file mode 100644 index 0000000..58bf2f1 --- /dev/null +++ b/isa/rv32uzbb/ctz.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctz.S +#----------------------------------------------------------------------------- +# +# Test ctz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctz, 32, 0x00000000); + TEST_R_OP( 3, ctz, 0, 0x00000001); + TEST_R_OP( 4, ctz, 0, 0x00000003); + + TEST_R_OP( 5, ctz, 15, 0xffff8000 ); + TEST_R_OP( 6, ctz, 23, 0x00800000 ); + TEST_R_OP( 7, ctz, 15, 0xffff8000 ); + + TEST_R_OP( 8, ctz, 0, 0x00007fff); + TEST_R_OP( 9, ctz, 0, 0x7fffffff); + TEST_R_OP( 10, ctz, 0, 0x0007ffff ); + + TEST_R_OP( 11, ctz, 31, 0x80000000); + TEST_R_OP( 12, ctz, 12, 0x121f5000); + + TEST_R_OP( 13, ctz, 30, 0xc0000000); + TEST_R_OP( 14, ctz, 1, 0x0000000e); + TEST_R_OP( 15, ctz, 0, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctz, 15, 0x007f8000 ); + TEST_R_OP( 22, ctz, 15, 0x00808000 ); + TEST_R_OP( 23, ctz, 12, 0x01809000 ); + + TEST_R_OP( 24, ctz, 0, 0x00007fff); + TEST_R_OP( 25, ctz, 0, 0x7fffffff); + TEST_R_OP( 26, ctz, 0, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/max.S b/isa/rv32uzbb/max.S new file mode 100644 index 0000000..ecd713c --- /dev/null +++ b/isa/rv32uzbb/max.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/max.S" diff --git a/isa/rv32uzbb/maxu.S b/isa/rv32uzbb/maxu.S new file mode 100644 index 0000000..27cfc29 --- /dev/null +++ b/isa/rv32uzbb/maxu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/maxu.S" diff --git a/isa/rv32uzbb/min.S b/isa/rv32uzbb/min.S new file mode 100644 index 0000000..c24a514 --- /dev/null +++ b/isa/rv32uzbb/min.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/min.S" diff --git a/isa/rv32uzbb/minu.S b/isa/rv32uzbb/minu.S new file mode 100644 index 0000000..4b2549d --- /dev/null +++ b/isa/rv32uzbb/minu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/minu.S" diff --git a/isa/rv32uzbb/orc_b.S b/isa/rv32uzbb/orc_b.S new file mode 100644 index 0000000..7fb8441 --- /dev/null +++ b/isa/rv32uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 3, orc.b, 0x000000ff, 0x00000001); + TEST_R_OP( 4, orc.b, 0x000000ff, 0x00000003); + + TEST_R_OP( 5, orc.b, 0xffffff00, 0xffff8000 ); + TEST_R_OP( 6, orc.b, 0x00ff0000, 0x00800000 ); + TEST_R_OP( 7, orc.b, 0xffffff00, 0xffff8000 ); + + TEST_R_OP( 8, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 9, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 10, orc.b, 0x00ffffff, 0x0007ffff ); + + TEST_R_OP( 11, orc.b, 0xff000000, 0x80000000); + TEST_R_OP( 12, orc.b, 0xffffff00, 0x121f5000); + + TEST_R_OP( 13, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 14, orc.b, 0x000000ff, 0x0000000e); + TEST_R_OP( 15, orc.b, 0xffffffff, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x00ffff00, 0x007f8000 ); + TEST_R_OP( 22, orc.b, 0x00ffff00, 0x00808000 ); + TEST_R_OP( 23, orc.b, 0xffffff00, 0x01808000 ); + + TEST_R_OP( 24, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 25, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 26, orc.b, 0x00ffffff, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/orn.S b/isa/rv32uzbb/orn.S new file mode 100644 index 0000000..cdfafcc --- /dev/null +++ b/isa/rv32uzbb/orn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/orn.S" diff --git a/isa/rv32uzbb/rev8.S b/isa/rv32uzbb/rev8.S new file mode 100644 index 0000000..2828f27 --- /dev/null +++ b/isa/rv32uzbb/rev8.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rev8.S +#----------------------------------------------------------------------------- +# +# Test rev8 instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 3, rev8, 0x01000000, 0x00000001); + TEST_R_OP( 4, rev8, 0x03000000, 0x00000003); + + TEST_R_OP( 5, rev8, 0x0080ffff, 0xffff8000 ); + TEST_R_OP( 6, rev8, 0x00008000, 0x00800000 ); + TEST_R_OP( 7, rev8, 0x0080ffff, 0xffff8000 ); + + TEST_R_OP( 8, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 9, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 10, rev8, 0xffff0700, 0x0007ffff ); + + TEST_R_OP( 11, rev8, 0x00000080, 0x80000000); + TEST_R_OP( 12, rev8, 0x00501f12, 0x121f5000); + + TEST_R_OP( 13, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 14, rev8, 0x0e000000, 0x0000000e); + TEST_R_OP( 15, rev8, 0x41134020, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d000000, 13); + TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b000000, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d000000, 13); + TEST_R_DEST_BYPASS( 29, 1, rev8, 0x13000000, 19); + TEST_R_DEST_BYPASS( 20, 2, rev8, 0x22000000, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, rev8, 0x00807f00, 0x007f8000 ); + TEST_R_OP( 22, rev8, 0x00808000, 0x00808000 ); + TEST_R_OP( 23, rev8, 0x00808001, 0x01808000 ); + + TEST_R_OP( 24, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 25, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 26, rev8, 0xffff0700, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/rol.S b/isa/rv32uzbb/rol.S new file mode 100644 index 0000000..a7c04fe --- /dev/null +++ b/isa/rv32uzbb/rol.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rol.S +#----------------------------------------------------------------------------- +# +# Test rol instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rol, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, rol, 0x00000002, 0x00000001, 1 ); + TEST_RR_OP( 4, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_OP( 5, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_OP( 6, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_OP( 7, rol, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, rol, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, rol, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, rol, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, rol, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, rol, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, rol, 0x42424242, 0x21212121, 1 ); + TEST_RR_OP( 14, rol, 0x90909090, 0x21212121, 7 ); + TEST_RR_OP( 15, rol, 0x48484848, 0x21212121, 14 ); + TEST_RR_OP( 16, rol, 0x90909090, 0x21212121, 31 ); + + # Verify that rotates only use bottom five bits + + TEST_RR_OP( 17, rol, 0x21212121, 0x21212121, 0xffffffe0 ); + TEST_RR_OP( 18, rol, 0x42424242, 0x21212121, 0xffffffe1 ); + TEST_RR_OP( 19, rol, 0x90909090, 0x21212121, 0xffffffe7 ); + TEST_RR_OP( 20, rol, 0x48484848, 0x21212121, 0xffffffee ); + TEST_RR_OP( 21, rol, 0x90909090, 0x21212121, 0xffffffff ); + + # Verify that rotates ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, rol, 0x12345678, 0x12345678, 0 ); + TEST_RR_OP( 45, rol, 0x23456781, 0x12345678, 4 ); + TEST_RR_OP( 46, rol, 0x92345678, 0x92345678, 0 ); + TEST_RR_OP( 47, rol, 0x93456789, 0x99345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rol, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rol, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rol, 0 ); + TEST_RR_ZERODEST( 43, rol, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/ror.S b/isa/rv32uzbb/ror.S new file mode 100644 index 0000000..5b57740 --- /dev/null +++ b/isa/rv32uzbb/ror.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test ror instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, ror, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, ror, 0x80000000, 0x00000001, 1 ); + TEST_RR_OP( 4, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_OP( 5, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_OP( 6, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_OP( 7, ror, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, ror, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, ror, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, ror, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, ror, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, ror, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, ror, 0x90909090, 0x21212121, 1 ); + TEST_RR_OP( 14, ror, 0x42424242, 0x21212121, 7 ); + TEST_RR_OP( 15, ror, 0x84848484, 0x21212121, 14 ); + TEST_RR_OP( 16, ror, 0x42424242, 0x21212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, ror, 0x21212121, 0x21212121, 0xffffffc0 ); + TEST_RR_OP( 18, ror, 0x90909090, 0x21212121, 0xffffffc1 ); + TEST_RR_OP( 19, ror, 0x42424242, 0x21212121, 0xffffffc7 ); + TEST_RR_OP( 20, ror, 0x84848484, 0x21212121, 0xffffffce ); + + TEST_RR_OP( 21, ror, 0x42424242, 0x21212121, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, ror, 0x60000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, ror, 0, 15 ); + TEST_RR_ZEROSRC2( 41, ror, 32, 32 ); + TEST_RR_ZEROSRC12( 42, ror, 0 ); + TEST_RR_ZERODEST( 43, ror, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/rori.S b/isa/rv32uzbb/rori.S new file mode 100644 index 0000000..c98ed85 --- /dev/null +++ b/isa/rv32uzbb/rori.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, rori, 0x00000001, 0x00000001, 0 ); + TEST_IMM_OP( 3, rori, 0x80000000, 0x00000001, 1 ); + TEST_IMM_OP( 4, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_OP( 5, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_OP( 6, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_OP( 7, rori, 0xffffffff, 0xffffffff, 0 ); + TEST_IMM_OP( 8, rori, 0xffffffff, 0xffffffff, 1 ); + TEST_IMM_OP( 9, rori, 0xffffffff, 0xffffffff, 7 ); + TEST_IMM_OP( 10, rori, 0xffffffff, 0xffffffff, 14 ); + TEST_IMM_OP( 11, rori, 0xffffffff, 0xffffffff, 31 ); + + TEST_IMM_OP( 12, rori, 0x21212121, 0x21212121, 0 ); + TEST_IMM_OP( 13, rori, 0x90909090, 0x21212121, 1 ); + TEST_IMM_OP( 14, rori, 0x42424242, 0x21212121, 7 ); + TEST_IMM_OP( 15, rori, 0x84848484, 0x21212121, 14 ); + TEST_IMM_OP( 16, rori, 0x42424242, 0x21212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x02000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, rori, 0, 31 ); + TEST_IMM_ZERODEST( 28, rori, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/sext_b.S b/isa/rv32uzbb/sext_b.S new file mode 100644 index 0000000..f73e107 --- /dev/null +++ b/isa/rv32uzbb/sext_b.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_b.S" diff --git a/isa/rv32uzbb/sext_h.S b/isa/rv32uzbb/sext_h.S new file mode 100644 index 0000000..d4b4206 --- /dev/null +++ b/isa/rv32uzbb/sext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_h.S" diff --git a/isa/rv32uzbb/xnor.S b/isa/rv32uzbb/xnor.S new file mode 100644 index 0000000..c5e453a --- /dev/null +++ b/isa/rv32uzbb/xnor.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/xnor.S" diff --git a/isa/rv32uzbb/zext_h.S b/isa/rv32uzbb/zext_h.S new file mode 100644 index 0000000..d339ccc --- /dev/null +++ b/isa/rv32uzbb/zext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/zext_h.S" diff --git a/isa/rv64uzbb/Makefrag b/isa/rv64uzbb/Makefrag new file mode 100644 index 0000000..2e93897 --- /dev/null +++ b/isa/rv64uzbb/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv64uzbb tests +#----------------------------------------------------------------------- + +rv64uzbb_sc_tests = \ + andn \ + clz clzw \ + cpop cpopw \ + ctz ctzw \ + max maxu \ + min minu \ + orc_b \ + orn \ + rev8 \ + rol rolw \ + ror rorw \ + rori roriw \ + sext_b sext_h \ + xnor \ + zext_h \ + +rv64uzbb_p_tests = $(addprefix rv64uzbb-p-, $(rv64uzbb_sc_tests)) +rv64uzbb_v_tests = $(addprefix rv64uzbb-v-, $(rv64uzbb_sc_tests)) +rv64uzbb_ps_tests = $(addprefix rv64uzbb-ps-, $(rv64uzbb_sc_tests)) + +spike_tests += $(rv64uzbb_p_tests) $(rv64uzbb_v_tests) diff --git a/isa/rv64uzbb/andn.S b/isa/rv64uzbb/andn.S new file mode 100644 index 0000000..be7f032 --- /dev/null +++ b/isa/rv64uzbb/andn.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# andn.S +#----------------------------------------------------------------------------- +# +# Test and instruction. +# This test is forked from and.S +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, andn, 0x00000000000f000f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, andn, 0x0f000f000f000f00, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, andn, 0x00f000f000f000f0, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, andn, 0x000f000f000f000f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_EQ_DEST( 8, andn, 0x0000000000000000, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, andn, 0, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, andn, 0x0000000000ff00ff, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, andn, 0 ); + TEST_RR_ZERODEST( 27, andn, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/clz.S b/isa/rv64uzbb/clz.S new file mode 100644 index 0000000..9df6531 --- /dev/null +++ b/isa/rv64uzbb/clz.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clz.S +#----------------------------------------------------------------------------- +# +# Test clz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clz, 64, 0x0000000000000000); + TEST_R_OP( 3, clz, 63, 0x0000000000000001); + TEST_R_OP( 4, clz, 62, 0x0000000000000003); + + TEST_R_OP( 5, clz, 0, 0xffffffffffff8000 ); + TEST_R_OP( 6, clz, 40, 0x0000000000800000 ); + TEST_R_OP( 7, clz, 13, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, clz, 49, 0x0000000000007fff); + TEST_R_OP( 9, clz, 33, 0x000000007fffffff); + TEST_R_OP( 10, clz, 45, 0x000000000007ffff ); + + TEST_R_OP( 11, clz, 0, 0xffffffff80000000); + TEST_R_OP( 12, clz, 8, 0x00ff578f121f5000); + + TEST_R_OP( 13, clz, 0, 0x8000000000000000); + TEST_R_OP( 14, clz, 60, 0x000000000000000e); + TEST_R_OP( 15, clz, 0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clz, 60, 13); + TEST_R_SRC1_EQ_DEST( 17, clz, 60, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clz, 60, 13); + TEST_R_DEST_BYPASS( 29, 1, clz, 59, 19); + TEST_R_DEST_BYPASS( 20, 2, clz, 58, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, clz, 37, 0x00000000070f8000 ); + TEST_R_OP( 22, clz, 36, 0x0000000008008000 ); + TEST_R_OP( 23, clz, 35, 0x0000000018008000 ); + + TEST_R_OP( 24, clz, 30, 0x0000000300007fff); + TEST_R_OP( 25, clz, 29, 0x000000077fffffff); + TEST_R_OP( 26, clz, 28, 0x0000000f0007ffff); + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/clzw.S b/isa/rv64uzbb/clzw.S new file mode 100644 index 0000000..24b659d --- /dev/null +++ b/isa/rv64uzbb/clzw.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clzw.S +#----------------------------------------------------------------------------- +# +# Test clzw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clzw, 32, 0x00000000); + TEST_R_OP( 3, clzw, 31, 0x00000001); + TEST_R_OP( 4, clzw, 30, 0x00000003); + + TEST_R_OP( 5, clzw, 0, 0xffff8000 ); + TEST_R_OP( 6, clzw, 8, 0x00800000 ); + TEST_R_OP( 7, clzw, 0, 0xffff8000 ); + + TEST_R_OP( 8, clzw, 17, 0x00007fff); + TEST_R_OP( 9, clzw, 1, 0x7fffffff); + TEST_R_OP( 10, clzw, 13, 0x0007ffff ); + + TEST_R_OP( 11, clzw, 0, 0x80000000); + TEST_R_OP( 12, clzw, 3, 0x121f5000); + + TEST_R_OP( 13, clzw, 5, 0x04000000); + TEST_R_OP( 14, clzw, 28, 0x0000000e); + TEST_R_OP( 15, clzw, 2, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clzw, 28, 13); + TEST_R_SRC1_EQ_DEST( 17, clzw, 28, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clzw, 28, 13); + TEST_R_DEST_BYPASS( 29, 1, clzw, 27, 19); + TEST_R_DEST_BYPASS( 20, 2, clzw, 26, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + + TEST_R_OP( 21, clzw, 5, 0x070f8000 ); + TEST_R_OP( 22, clzw, 4, 0x08008000 ); + TEST_R_OP( 23, clzw, 3, 0x18008000 ); + + TEST_R_OP( 24, clzw, 17, 0x00007fff); + TEST_R_OP( 25, clzw, 1, 0x7fffffff); + TEST_R_OP( 26, clzw, 13, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/cpop.S b/isa/rv64uzbb/cpop.S new file mode 100644 index 0000000..0083a1a --- /dev/null +++ b/isa/rv64uzbb/cpop.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpop.S +#----------------------------------------------------------------------------- +# +# Test cpop instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpop, 0, 0x0000000000000000); + TEST_R_OP( 3, cpop, 1, 0x0000000000000001); + TEST_R_OP( 4, cpop, 2, 0x0000000000000003); + + TEST_R_OP( 5, cpop, 49, 0xffffffffffff8000 ); + TEST_R_OP( 6, cpop, 1, 0x0000000000800000 ); + TEST_R_OP( 7, cpop, 34, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, cpop, 15, 0x0000000000007fff); + TEST_R_OP( 9, cpop, 31, 0x000000007fffffff); + TEST_R_OP( 10, cpop, 19, 0x000000000007ffff ); + + TEST_R_OP( 11, cpop, 33, 0xffffffff80000000); + TEST_R_OP( 12, cpop, 27, 0x00ff578f121f5000); + + TEST_R_OP( 13, cpop, 1, 0x8000000000000000); + TEST_R_OP( 14, cpop, 3, 0x000000000000000e); + TEST_R_OP( 15, cpop, 11, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpop, 8, 0x00000000007f8000 ); + TEST_R_OP( 22, cpop, 2, 0x0000000000808000 ); + TEST_R_OP( 23, cpop, 3, 0x0000000001808000 ); + + TEST_R_OP( 24, cpop, 17, 0x0000000300007fff); + TEST_R_OP( 25, cpop, 34, 0x000000077fffffff); + TEST_R_OP( 26, cpop, 23, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/cpopw.S b/isa/rv64uzbb/cpopw.S new file mode 100644 index 0000000..7b73882 --- /dev/null +++ b/isa/rv64uzbb/cpopw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpopw.S +#----------------------------------------------------------------------------- +# +# Test cpopw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpopw, 0, 0x00000000); + TEST_R_OP( 3, cpopw, 1, 0x00000001); + TEST_R_OP( 4, cpopw, 2, 0x00000003); + + TEST_R_OP( 5, cpopw, 17, 0xffff8000 ); + TEST_R_OP( 6, cpopw, 1, 0x00800000 ); + TEST_R_OP( 7, cpopw, 18, 0xffff6000 ); + + TEST_R_OP( 8, cpopw, 15, 0x00007fff); + TEST_R_OP( 9, cpopw, 31, 0x7fffffff); + TEST_R_OP( 10, cpopw, 19, 0x0007ffff ); + + TEST_R_OP( 11, cpopw, 1, 0x80000000); + TEST_R_OP( 12, cpopw, 9, 0x121f5000); + + TEST_R_OP( 13, cpopw, 0, 0x00000000); + TEST_R_OP( 14, cpopw, 3, 0x0000000e); + TEST_R_OP( 15, cpopw, 7, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpopw, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpopw, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpopw, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpopw, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpopw, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpopw, 8, 0x007f8000 ); + TEST_R_OP( 22, cpopw, 2, 0x00808000 ); + TEST_R_OP( 23, cpopw, 3, 0x01808000 ); + + TEST_R_OP( 24, cpopw, 17, 0x30007fff); + TEST_R_OP( 25, cpopw, 30, 0x77ffffff); + TEST_R_OP( 26, cpopw, 19, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/ctz.S b/isa/rv64uzbb/ctz.S new file mode 100644 index 0000000..21b2426 --- /dev/null +++ b/isa/rv64uzbb/ctz.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctz.S +#----------------------------------------------------------------------------- +# +# Test ctz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctz, 64, 0x0000000000000000); + TEST_R_OP( 3, ctz, 0, 0x0000000000000001); + TEST_R_OP( 4, ctz, 0, 0x0000000000000003); + + TEST_R_OP( 5, ctz, 15, 0xffffffffffff8000 ); + TEST_R_OP( 6, ctz, 23, 0x0000000000800000 ); + TEST_R_OP( 7, ctz, 15, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, ctz, 0, 0x0000000000007fff); + TEST_R_OP( 9, ctz, 0, 0x000000007fffffff); + TEST_R_OP( 10, ctz, 0, 0x000000000007ffff ); + + TEST_R_OP( 11, ctz, 31, 0xffffffff80000000); + TEST_R_OP( 12, ctz, 12, 0x00ff578f121f5000); + + TEST_R_OP( 13, ctz, 63, 0x8000000000000000); + TEST_R_OP( 14, ctz, 1, 0x000000000000000e); + TEST_R_OP( 15, ctz, 0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctz, 15, 0x00000000007f8000 ); + TEST_R_OP( 22, ctz, 15, 0x0000000000808000 ); + TEST_R_OP( 23, ctz, 12, 0x0000000001809000 ); + + TEST_R_OP( 24, ctz, 0, 0x0000000300007fff); + TEST_R_OP( 25, ctz, 0, 0x000000077fffffff); + TEST_R_OP( 26, ctz, 0, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/ctzw.S b/isa/rv64uzbb/ctzw.S new file mode 100644 index 0000000..9915bf1 --- /dev/null +++ b/isa/rv64uzbb/ctzw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctzw.S +#----------------------------------------------------------------------------- +# +# Test ctzw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctzw, 32, 0x00000000); + TEST_R_OP( 3, ctzw, 0, 0x00000001); + TEST_R_OP( 4, ctzw, 0, 0x00000003); + + TEST_R_OP( 5, ctzw, 15, 0xffff8000 ); + TEST_R_OP( 6, ctzw, 23, 0x00800000 ); + TEST_R_OP( 7, ctzw, 15, 0xffff8000 ); + + TEST_R_OP( 8, ctzw, 0, 0x00007fff); + TEST_R_OP( 9, ctzw, 0, 0x7fffffff); + TEST_R_OP( 10, ctzw, 0, 0x0007ffff ); + + TEST_R_OP( 11, ctzw, 31, 0x80000000); + TEST_R_OP( 12, ctzw, 12, 0x121f5000); + + TEST_R_OP( 13, ctzw, 30, 0xc0000000); + TEST_R_OP( 14, ctzw, 1, 0x0000000e); + TEST_R_OP( 15, ctzw, 0, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctzw, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctzw, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctzw, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctzw, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctzw, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctzw, 15, 0x007f8000 ); + TEST_R_OP( 22, ctzw, 15, 0x00808000 ); + TEST_R_OP( 23, ctzw, 12, 0x01809000 ); + + TEST_R_OP( 24, ctzw, 0, 0x00007fff); + TEST_R_OP( 25, ctzw, 0, 0x7fffffff); + TEST_R_OP( 26, ctzw, 0, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/max.S b/isa/rv64uzbb/max.S new file mode 100644 index 0000000..92eb9ad --- /dev/null +++ b/isa/rv64uzbb/max.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# max.S +#----------------------------------------------------------------------------- +# +# Test max instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, max, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, max, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, max, 0x0000000000000007, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, max, 0x0000000000000007, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, max, 0x0000000000000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, max, 0xffffffffffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, max, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, max, 0x0000000000007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, max, 0x000000007fffffff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, max, 0x0000000000000001, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, max, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, max, 14, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, max, 13, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, max, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, max, 13, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, max, 14, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, max, 13, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, max, 14, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, max, 13, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, max, 15, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, max, 13, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, max, 16, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, max, 13, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, max, 17, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, max, 13, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, max, 18, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, max, 13, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, max, 19, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, max, 13, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, max, 0, -1 ); + TEST_RR_ZEROSRC2( 36, max, 0, -1 ); + TEST_RR_ZEROSRC12( 37, max, 0 ); + TEST_RR_ZERODEST( 38, max, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/maxu.S b/isa/rv64uzbb/maxu.S new file mode 100644 index 0000000..78c2055 --- /dev/null +++ b/isa/rv64uzbb/maxu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# maxu.S +#----------------------------------------------------------------------------- +# +# Test maxu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, maxu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, maxu, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, maxu, 0x00000007, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, maxu, 0x00000007, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, maxu, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, maxu, 0x80000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, maxu, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, maxu, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, maxu, 0x7fffffff, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, maxu, 0x7fffffff, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, maxu, 0x80000000, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, maxu, 0xffff8000, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, maxu, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, maxu, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, maxu, 0xffffffff, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, maxu, 14, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, maxu, 13, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, maxu, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, maxu, 13, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, maxu, 14, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, maxu, 13, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, maxu, 14, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, maxu, 13, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, maxu, 15, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, maxu, 13, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, maxu, 16, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, maxu, 13, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, maxu, 17, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, maxu, 13, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, maxu, 18, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, maxu, 13, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, maxu, 19, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, maxu, 13, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, maxu, -1, -1 ); + TEST_RR_ZEROSRC2( 36, maxu, -1, -1 ); + TEST_RR_ZEROSRC12( 37, maxu, 0 ); + TEST_RR_ZERODEST( 38, maxu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/min.S b/isa/rv64uzbb/min.S new file mode 100644 index 0000000..d2e3e29 --- /dev/null +++ b/isa/rv64uzbb/min.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# min.S +#----------------------------------------------------------------------------- +# +# Test min instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, min, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, min, 0x0000000000000003, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, min, 0x0000000000000003, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, min, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, min, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, min, 0x0000000000000000, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, min, 0x0000000000007fff, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, min, 0xffffffffffff8000, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, min, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, min, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, min, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, min, 13, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, min, 11, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, min, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, min, 11, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, min, 13, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, min, 12, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, min, 13, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, min, 11, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, min, 13, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, min, 10, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, min, 13, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, min, 9, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, min, 13, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, min, 8, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, min, 13, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, min, 7, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, min, 13, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, min, 6, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, min, -1, -1 ); + TEST_RR_ZEROSRC2( 36, min, -1, -1 ); + TEST_RR_ZEROSRC12( 37, min, 0 ); + TEST_RR_ZERODEST( 38, min, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/minu.S b/isa/rv64uzbb/minu.S new file mode 100644 index 0000000..f92859a --- /dev/null +++ b/isa/rv64uzbb/minu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# minu.S +#----------------------------------------------------------------------------- +# +# Test minu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, minu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, minu, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, minu, 0x00000003, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, minu, 0x00000003, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, minu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, minu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, minu, 0x80000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, minu, 0x00000000, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, minu, 0x00000000, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, minu, 0x00007fff, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, minu, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, minu, 0x7fffffff, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, minu, 0x00000000, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, minu, 0x00000001, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, minu, 0xffffffff, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, minu, 13, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, minu, 11, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, minu, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, minu, 11, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, minu, 13, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, minu, 12, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, minu, 13, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, minu, 11, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, minu, 13, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, minu, 10, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, minu, 13, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, minu, 9, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, minu, 13, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, minu, 8, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, minu, 13, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, minu, 7, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, minu, 13, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, minu, 6, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, minu, 0, -1 ); + TEST_RR_ZEROSRC2( 36, minu, 0, -1 ); + TEST_RR_ZEROSRC12( 37, minu, 0 ); + TEST_RR_ZERODEST( 38, minu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/orc_b.S b/isa/rv64uzbb/orc_b.S new file mode 100644 index 0000000..b236bd3 --- /dev/null +++ b/isa/rv64uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, orc.b, 0x00000000000000ff, 0x0000000000000001); + TEST_R_OP( 4, orc.b, 0x00000000000000ff, 0x0000000000000003); + + TEST_R_OP( 5, orc.b, 0xffffffffffffff00, 0xffffffffffff8000 ); + TEST_R_OP( 6, orc.b, 0x0000000000ff0000, 0x0000000000800000 ); + TEST_R_OP( 7, orc.b, 0x00ffffffffffff00, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, orc.b, 0x000000000000ffff, 0x0000000000007fff); + TEST_R_OP( 9, orc.b, 0x00000000ffffffff, 0x000000007fffffff); + TEST_R_OP( 10, orc.b, 0x0000000000ffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, orc.b, 0xffffffffff000000, 0xffffffff80000000); + TEST_R_OP( 12, orc.b, 0x00ffffffffffff00, 0x00ff578f121f5000); + + TEST_R_OP( 13, orc.b, 0xff00000000000000, 0x8000000000000000); + TEST_R_OP( 14, orc.b, 0x00000000000000ff, 0x000000000000000e); + TEST_R_OP( 15, orc.b, 0xff0000ffffffffff, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x0000000000ffff00, 0x00000000007f8000 ); + TEST_R_OP( 22, orc.b, 0x0000000000ffff00, 0x0000000000808000 ); + TEST_R_OP( 23, orc.b, 0x00000000ffffff00, 0x0000000001808000 ); + + TEST_R_OP( 24, orc.b, 0x000000ff0000ffff, 0x0000000300007fff); + TEST_R_OP( 25, orc.b, 0x000000ffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, orc.b, 0x000000ff00ffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/orn.S b/isa/rv64uzbb/orn.S new file mode 100644 index 0000000..b610007 --- /dev/null +++ b/isa/rv64uzbb/orn.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orn.S +#----------------------------------------------------------------------------- +# +# Test orn instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, orn, 0xffffffffff0fff0f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, orn, 0x0fff0fff0fff0fff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, orn, 0xf0fff0fff0fff0ff, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, orn, 0xff0fff0fff0fff0f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, orn, 0xffffffffffffffff, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, orn, 0x0000000000ff00ff, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, orn, -1, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, orn, -1 ); + TEST_RR_ZERODEST( 27, orn, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rev8.S b/isa/rv64uzbb/rev8.S new file mode 100644 index 0000000..5e65f37 --- /dev/null +++ b/isa/rv64uzbb/rev8.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rev8.S +#----------------------------------------------------------------------------- +# +# Test rev8 instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, rev8, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, rev8, 0x0100000000000000, 0x0000000000000001); + TEST_R_OP( 4, rev8, 0x0300000000000000, 0x0000000000000003); + + TEST_R_OP( 5, rev8, 0x0080ffffffffffff, 0xffffffffffff8000 ); + TEST_R_OP( 6, rev8, 0x0000800000000000, 0x0000000000800000 ); + TEST_R_OP( 7, rev8, 0x0080ffffffff0400, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, rev8, 0xff7f000000000000, 0x0000000000007fff); + TEST_R_OP( 9, rev8, 0xffffff7f00000000, 0x000000007fffffff); + TEST_R_OP( 10, rev8, 0xffff070000000000, 0x000000000007ffff ); + + TEST_R_OP( 11, rev8, 0x00000080ffffffff, 0xffffffff80000000); + TEST_R_OP( 12, rev8, 0x00501f128f57ff00, 0x00ff578f121f5000); + + TEST_R_OP( 13, rev8, 0x0000000000000080, 0x8000000000000000); + TEST_R_OP( 14, rev8, 0x0e00000000000000, 0x000000000000000e); + TEST_R_OP( 15, rev8, 0x41134020030000a0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d00000000000000, 13); + TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b00000000000000, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d00000000000000, 13); + TEST_R_DEST_BYPASS( 29, 1, rev8, 0x1300000000000000, 19); + TEST_R_DEST_BYPASS( 20, 2, rev8, 0x2200000000000000, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, rev8, 0x00807f0000000000, 0x00000000007f8000 ); + TEST_R_OP( 22, rev8, 0x0080800000000000, 0x0000000000808000 ); + TEST_R_OP( 23, rev8, 0x0080800100000000, 0x0000000001808000 ); + + TEST_R_OP( 24, rev8, 0xff7f000003000000, 0x0000000300007fff); + TEST_R_OP( 25, rev8, 0xffffff7f07000000, 0x000000077fffffff); + TEST_R_OP( 26, rev8, 0xffff07000f000000, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rol.S b/isa/rv64uzbb/rol.S new file mode 100644 index 0000000..a69bc05 --- /dev/null +++ b/isa/rv64uzbb/rol.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rol.S +#----------------------------------------------------------------------------- +# +# Test rol instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rol, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rol, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rol, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rol, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rol, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rol, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rol, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rol, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rol, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rol, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rol, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rol, 0x1090909080000000, 0x0000000021212121, 31 ); + + # Verify that rotates only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, rol, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, rol, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, rol, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, rol, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, rol, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, rol, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, rol, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, rol, 0x0909080000000109, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rol, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rol, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rol, 0 ); + TEST_RR_ZERODEST( 43, rol, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rolw.S b/isa/rv64uzbb/rolw.S new file mode 100644 index 0000000..fdf4674 --- /dev/null +++ b/isa/rv64uzbb/rolw.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rolw.S +#----------------------------------------------------------------------------- +# +# Test rolw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rolw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rolw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rolw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rolw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rolw, 0xffffffff90909090, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rolw, 0x0000000048484848, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rolw, 0xffffffff90909090, 0x0000000021212121, 31 ); + + # Verify that rotates only use bottom five bits + + TEST_RR_OP( 17, rolw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, rolw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, rolw, 0x0000000048484848, 0x0000000021212121, 0xffffffffffffffee ); + TEST_RR_OP( 21, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffff ); + + # Verify that rotates ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, rolw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, rolw, 0x0000000023456781, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, rolw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, rolw, 0xffffffff93456789, 0x0000000099345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rolw, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rolw, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rolw, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rolw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rolw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rolw, 0 ); + TEST_RR_ZERODEST( 43, rolw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/ror.S b/isa/rv64uzbb/ror.S new file mode 100644 index 0000000..163333d --- /dev/null +++ b/isa/rv64uzbb/ror.S @@ -0,0 +1,94 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test ror instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, ror, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, ror, 0x8000000000000000, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, ror, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, ror, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, ror, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, ror, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, ror, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, ror, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, ror, 0x8000000010909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, ror, 0x4200000000424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, ror, 0x8484000000008484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, ror, 0x4242424200000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, ror, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, ror, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, ror, 0x4200000000424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, ror, 0x8484000000008484, 0x0000000021212121, 0xffffffffffffffce ); + + TEST_RR_OP( 21, ror, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, ror, 0x0000000000000002, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, ror, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, ror, 0x0004242424200000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, ror, 0x0200000000000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, ror, 0x0004000000000000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, ror, 0x6000000000000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, ror, 0, 15 ); + TEST_RR_ZEROSRC2( 41, ror, 32, 32 ); + TEST_RR_ZEROSRC12( 42, ror, 0 ); + TEST_RR_ZERODEST( 43, ror, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rori.S b/isa/rv64uzbb/rori.S new file mode 100644 index 0000000..153f8e6 --- /dev/null +++ b/isa/rv64uzbb/rori.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, rori, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, rori, 0x8000000000000000, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, rori, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, rori, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, rori, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, rori, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, rori, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, rori, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, rori, 0x8000000010909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, rori, 0x4200000000424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, rori, 0x8484000000008484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, rori, 0x4242424200000000, 0x0000000021212121, 31 ); + + TEST_IMM_OP( 17, rori, 0x0000000000000002, 0x0000000000000001, 63 ); + TEST_IMM_OP( 18, rori, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 19, rori, 0x0004242424200000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x0200000000000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, rori, 0, 31 ); + TEST_IMM_ZERODEST( 28, rori, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/roriw.S b/isa/rv64uzbb/roriw.S new file mode 100644 index 0000000..44f3819 --- /dev/null +++ b/isa/rv64uzbb/roriw.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, roriw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, roriw, 0xffffffff80000000, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, roriw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, roriw, 0xffffffff90909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, roriw, 0x0000000042424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, roriw, 0xffffffff84848484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, roriw, 0x0000000042424242, 0x0000000021212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, roriw, 0x0000000002000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, roriw, 0, 31 ); + TEST_IMM_ZERODEST( 28, roriw, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rorw.S b/isa/rv64uzbb/rorw.S new file mode 100644 index 0000000..de11c3c --- /dev/null +++ b/isa/rv64uzbb/rorw.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rorw.S +#----------------------------------------------------------------------------- +# +# Test rorw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rorw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rorw, 0xffffffff80000000, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rorw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rorw, 0xffffffff90909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rorw, 0x0000000042424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rorw, 0xffffffff84848484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rorw, 0x0000000042424242, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, rorw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, rorw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, rorw, 0xffffffff84848484, 0x0000000021212121, 0xffffffffffffffce ); + + TEST_RR_OP( 21, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rorw, 0x0000000002000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rorw, 0x0000000000040000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rorw, 0x0000000060000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rorw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rorw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rorw, 0 ); + TEST_RR_ZERODEST( 43, rorw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/sext_b.S b/isa/rv64uzbb/sext_b.S new file mode 100644 index 0000000..8acf86a --- /dev/null +++ b/isa/rv64uzbb/sext_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_b.S +#----------------------------------------------------------------------------- +# +# Test sext.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, sext.b, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, sext.b, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, sext.b, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, sext.b, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_R_OP( 6, sext.b, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, sext.b, 0x0000000000000000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, sext.b, 0xffffffffffffffff, 0x0000000000007fff); + TEST_R_OP( 9, sext.b, 0xffffffffffffffff, 0x000000007fffffff); + TEST_R_OP( 10, sext.b, 0xffffffffffffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, sext.b, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, sext.b, 0x0000000000000000, 0x00ff578f121f5000); + + TEST_R_OP( 13, sext.b, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, sext.b, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, sext.b, 0x0000000000000041, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, sext.b, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, sext.b, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, sext.b, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, sext.b, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, sext.b, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, sext.b, 0x0000000000000000, 0x00000000007f8000 ); + TEST_R_OP( 22, sext.b, 0x0000000000000000, 0x0000000000808000 ); + TEST_R_OP( 23, sext.b, 0x0000000000000000, 0x0000000001808000 ); + + TEST_R_OP( 24, sext.b, 0xffffffffffffffff, 0x0000000300007fff); + TEST_R_OP( 25, sext.b, 0xffffffffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, sext.b, 0xffffffffffffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/sext_h.S b/isa/rv64uzbb/sext_h.S new file mode 100644 index 0000000..59cf386 --- /dev/null +++ b/isa/rv64uzbb/sext_h.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_h.S +#----------------------------------------------------------------------------- +# +# Test sext.h instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, sext.h, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, sext.h, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, sext.h, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, sext.h, 0xffffffffffff8000, 0xffffffffffff8000 ); + TEST_R_OP( 6, sext.h, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, sext.h, 0xffffffffffff8000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, sext.h, 0x0000000000007fff, 0x0000000000007fff); + TEST_R_OP( 9, sext.h, 0xffffffffffffffff, 0x000000007fffffff); + TEST_R_OP( 10, sext.h, 0xffffffffffffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, sext.h, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, sext.h, 0x0000000000005000, 0x00ff578f121f5000); + + TEST_R_OP( 13, sext.h, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, sext.h, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, sext.h, 0x0000000000001341, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, sext.h, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, sext.h, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, sext.h, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, sext.h, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, sext.h, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, sext.h, 0xffffffffffff8000, 0x00000000007f8000 ); + TEST_R_OP( 22, sext.h, 0xffffffffffff8000, 0x0000000000808000 ); + TEST_R_OP( 23, sext.h, 0xffffffffffff8000, 0x0000000001808000 ); + + TEST_R_OP( 24, sext.h, 0x0000000000007fff, 0x0000000300007fff); + TEST_R_OP( 25, sext.h, 0xffffffffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, sext.h, 0xffffffffffffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/xnor.S b/isa/rv64uzbb/xnor.S new file mode 100644 index 0000000..5a74f86 --- /dev/null +++ b/isa/rv64uzbb/xnor.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xnor.S +#----------------------------------------------------------------------------- +# +# Test xnor instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, xnor, 0xffffffffff00ff00, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, xnor, 0x00ff00ff00ff00ff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, xnor, 0xf00ff00ff00ff00f, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, xnor, 0xff00ff00ff00ff00, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, xnor, 0xffffffffffffffff, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, xnor, 0x0000000000ff00ff, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, xnor, 0xffffffffff00ff00, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, xnor, -1 ); + TEST_RR_ZERODEST( 27, xnor, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/zext_h.S b/isa/rv64uzbb/zext_h.S new file mode 100644 index 0000000..baa0b7a --- /dev/null +++ b/isa/rv64uzbb/zext_h.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_h.S +#----------------------------------------------------------------------------- +# +# Test zext.h instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, zext.h, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, zext.h, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, zext.h, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, zext.h, 0x0000000000008000, 0xffffffffffff8000 ); + TEST_R_OP( 6, zext.h, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, zext.h, 0x0000000000008000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, zext.h, 0x0000000000007fff, 0x0000000000007fff); + TEST_R_OP( 9, zext.h, 0x000000000000ffff, 0x000000007fffffff); + TEST_R_OP( 10, zext.h, 0x000000000000ffff, 0x000000000007ffff ); + + TEST_R_OP( 11, zext.h, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, zext.h, 0x0000000000005000, 0x00ff578f121f5000); + + TEST_R_OP( 13, zext.h, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, zext.h, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, zext.h, 0x0000000000001341, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, zext.h, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, zext.h, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, zext.h, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, zext.h, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, zext.h, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, zext.h, 0x0000000000008000, 0x00000000007f8000 ); + TEST_R_OP( 22, zext.h, 0x0000000000008000, 0x0000000000808000 ); + TEST_R_OP( 23, zext.h, 0x0000000000008000, 0x0000000001808000 ); + + TEST_R_OP( 24, zext.h, 0x0000000000007fff, 0x0000000300007fff); + TEST_R_OP( 25, zext.h, 0x000000000000ffff, 0x000000077fffffff); + TEST_R_OP( 26, zext.h, 0x000000000000ffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |