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| author | Andrew Waterman <andrew@sifive.com> | 2024-02-18 20:16:38 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-02-18 20:16:58 -0800 |
| commit | 36b18c8e4ea7bdcd30aed03c5d6235fbb0f8213c (patch) | |
| tree | 9d854dfd030e013064f9940739ef4f4b8942e23f | |
| parent | 3bd02c8ab45666cf1c0532294f115c4d2ce3e027 (diff) | |
| download | riscv-tests-36b18c8e4ea7bdcd30aed03c5d6235fbb0f8213c.zip riscv-tests-36b18c8e4ea7bdcd30aed03c5d6235fbb0f8213c.tar.gz riscv-tests-36b18c8e4ea7bdcd30aed03c5d6235fbb0f8213c.tar.bz2 | |
Fix breakpoint test
See https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 1223f71..153963a 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -26,6 +26,9 @@ RVTEST_CODE_BEGIN 1: csrw mtvec, a0 + # Enable interrupts; see https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214 + csrsi mstatus, MSTATUS_MIE + # Skip tselect if hard-wired. csrw tselect, x0 csrr a1, tselect |