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| author | Lucas Clemente Vella <lucas.vella@powdrlabs.com> | 2024-01-29 19:40:50 +0000 |
|---|---|---|
| committer | Lucas Clemente Vella <lucas.vella@powdrlabs.com> | 2024-01-29 19:44:33 +0000 |
| commit | a0771484353d273bd6df8389193df9597b105572 (patch) | |
| tree | 43cee9ab73a6b03c5be6dbf75fd536ec3737e052 | |
| parent | bd0a19c136927eaa3b7296a591a896c141affb6b (diff) | |
| download | riscv-tests-a0771484353d273bd6df8389193df9597b105572.zip riscv-tests-a0771484353d273bd6df8389193df9597b105572.tar.gz riscv-tests-a0771484353d273bd6df8389193df9597b105572.tar.bz2 | |
Uses appropriate addi instruction in lrsc test.
| -rw-r--r-- | isa/rv64ua/lrsc.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S index ab0d025..39fb156 100644 --- a/isa/rv64ua/lrsc.S +++ b/isa/rv64ua/lrsc.S @@ -62,7 +62,7 @@ addi a2, a2, 1 add a4, a4, a2 sc.w a4, a4, (a0) bnez a4, 1b -add a1, a1, -1 +addi a1, a1, -1 bnez a1, 1b # wait for all cores to finish |