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| author | zilong <zl123338@gmail.com> | 2024-04-17 11:25:09 +0800 |
|---|---|---|
| committer | zilong <zl123338@gmail.com> | 2024-04-17 11:25:09 +0800 |
| commit | 7f454c3d8aefb1d90727a3db7f13ac691640a575 (patch) | |
| tree | 5b2841210e57bfedee26fa8c27cad1632f800432 | |
| parent | 6b1d7372d951ed75811e0a09c0fe9e065c141c2d (diff) | |
| download | riscv-tests-7f454c3d8aefb1d90727a3db7f13ac691640a575.zip riscv-tests-7f454c3d8aefb1d90727a3db7f13ac691640a575.tar.gz riscv-tests-7f454c3d8aefb1d90727a3db7f13ac691640a575.tar.bz2 | |
debug: Fix nonexistent trigger registers trap handle in entry.S
| -rwxr-xr-x | debug/programs/entry.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 09cad53..5c281a6 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -84,8 +84,9 @@ handle_reset: beq t0, t1, 1b .p2align 2 2: - # Restore mtvec + # Restore mtvec and mstatus csrw mtvec, t2 + csrwi mstatus, 0 #ifdef MULTICORE csrr t0, CSR_MHARTID |