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| author | Andrew Waterman <andrew@sifive.com> | 2024-03-19 14:14:31 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-03-19 14:14:31 -0700 |
| commit | fd01e46314636666b5bed1f08465f734751a4cda (patch) | |
| tree | 9147a0b4d5362078dc0eb9e7df2b19d641b99207 | |
| parent | 06ca28cb085a1b5c572dc90e941d674a72e41353 (diff) | |
| download | riscv-tests-fd01e46314636666b5bed1f08465f734751a4cda.zip riscv-tests-fd01e46314636666b5bed1f08465f734751a4cda.tar.gz riscv-tests-fd01e46314636666b5bed1f08465f734751a4cda.tar.bz2 | |
ma_addr: permit access faults in lieu of misaligned exceptions
| -rw-r--r-- | isa/rv64mi/ma_addr.S | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index f02a1af..8579c01 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -20,6 +20,7 @@ RVTEST_CODE_BEGIN # indicate it's a load test li s1, CAUSE_MISALIGNED_LOAD + li s2, CAUSE_LOAD_ACCESS #define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1))) @@ -56,6 +57,7 @@ RVTEST_CODE_BEGIN # indicate it's a store test li s1, CAUSE_MISALIGNED_STORE + li s2, CAUSE_STORE_ACCESS /* Check that a misaligned store has some effect and takes no exception, or takes no effect and generates an exception. This is not very @@ -96,7 +98,10 @@ RVTEST_CODE_BEGIN .global mtvec_handler mtvec_handler: csrr t0, mcause - bne t0, s1, fail + beq t0, s1, 1f + beq t0, s2, 1f + j fail +1: csrr t0, mbadaddr beqz t0, 1f |