Add zba test cases

Signed-off-by: Roger Chang <rogerycchang@google.com>

14 files changed, 958 insertions, 2 deletions

diff --git a/isa/Makefile b/isa/Makefile
index d66b901..ffd82ff 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -14,6 +14,7 @@ include $(src_dir)/rv64ua/Makefrag
 include $(src_dir)/rv64uf/Makefrag
 include $(src_dir)/rv64ud/Makefrag
 include $(src_dir)/rv64uzfh/Makefrag
+include $(src_dir)/rv64uzba/Makefrag
 include $(src_dir)/rv64si/Makefrag
 include $(src_dir)/rv64ssvnapot/Makefrag
 include $(src_dir)/rv64mi/Makefrag
@@ -26,6 +27,7 @@ include $(src_dir)/rv32ua/Makefrag
 include $(src_dir)/rv32uf/Makefrag
 include $(src_dir)/rv32ud/Makefrag
 include $(src_dir)/rv32uzfh/Makefrag
+include $(src_dir)/rv32uzba/Makefrag
 include $(src_dir)/rv32si/Makefrag
 include $(src_dir)/rv32mi/Makefrag
 
@@ -50,10 +52,10 @@ vpath %.S $(src_dir)
 	$(RISCV_OBJDUMP) $< > $@
 
 %.out: %
-	$(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@
+	$(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@
 
 %.out32: %
-	$(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@
+	$(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@
 
 define compile_template
 
@@ -86,6 +88,7 @@ $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32))
+$(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32))
 $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32))
 ifeq ($(XLEN),64)
@@ -96,6 +99,7 @@ $(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64))
+$(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64))
 $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64))
 $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64))
diff --git a/isa/rv32uzba/Makefrag b/isa/rv32uzba/Makefrag
new file mode 100644
index 0000000..39a2c99
--- /dev/null
+++ b/isa/rv32uzba/Makefrag
@@ -0,0 +1,14 @@
+#=======================================================================
+# Makefrag for rv32uzba tests
+#-----------------------------------------------------------------------
+
+rv32uzba_sc_tests = \
+	sh1add \
+	sh2add \
+	sh3add \
+
+rv32uzba_p_tests = $(addprefix rv32uzba-p-, $(rv32uzba_sc_tests))
+rv32uzba_v_tests = $(addprefix rv32uzba-v-, $(rv32uzba_sc_tests))
+rv32uzba_ps_tests = $(addprefix rv32uzba-ps-, $(rv32uzba_sc_tests))
+
+spike_tests += $(rv32uzba_p_tests) $(rv32uzba_v_tests)
diff --git a/isa/rv32uzba/sh1add.S b/isa/rv32uzba/sh1add.S
new file mode 100644
index 0000000..03ae190
--- /dev/null
+++ b/isa/rv32uzba/sh1add.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh1add.S
+#-----------------------------------------------------------------------------
+#
+# Test sh1add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sh1add, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sh1add, 0x00000003, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sh1add, 0x0000000d, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sh1add, 0xffff8000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  sh1add, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sh1add, 0xffff8000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP( 8,  sh1add, 0x00007fff, 0x00000000, 0x00007fff );
+  TEST_RR_OP( 9,  sh1add, 0xfffffffe, 0x7fffffff, 0x00000000 );
+  TEST_RR_OP( 10, sh1add, 0x00007ffd, 0x7fffffff, 0x00007fff );
+
+  TEST_RR_OP( 11, sh1add, 0x00007fff, 0x80000000, 0x00007fff );
+  TEST_RR_OP( 12, sh1add, 0xffff7ffe, 0x7fffffff, 0xffff8000 );
+
+  TEST_RR_OP( 13, sh1add, 0xffffffff, 0x00000000, 0xffffffff );
+  TEST_RR_OP( 14, sh1add, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP( 15, sh1add, 0xfffffffd, 0xffffffff, 0xffffffff );
+
+  TEST_RR_OP( 16, sh1add, 0x80000001, 0x00000001, 0x7fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 );
+  TEST_RR_ZEROSRC12( 37, sh1add, 0 );
+  TEST_RR_ZERODEST( 38, sh1add, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32uzba/sh2add.S b/isa/rv32uzba/sh2add.S
new file mode 100644
index 0000000..057dba5
--- /dev/null
+++ b/isa/rv32uzba/sh2add.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh2add.S
+#-----------------------------------------------------------------------------
+#
+# Test sh2add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sh2add, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sh2add, 0x00000005, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sh2add, 0x00000013, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sh2add, 0xffff8000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  sh2add, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sh2add, 0xffff8000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP( 8,  sh2add, 0x00007fff, 0x00000000, 0x00007fff );
+  TEST_RR_OP( 9,  sh2add, 0xfffffffc, 0x7fffffff, 0x00000000 );
+  TEST_RR_OP( 10, sh2add, 0x00007ffb, 0x7fffffff, 0x00007fff );
+
+  TEST_RR_OP( 11, sh2add, 0x00007fff, 0x80000000, 0x00007fff );
+  TEST_RR_OP( 12, sh2add, 0xffff7ffc, 0x7fffffff, 0xffff8000 );
+
+  TEST_RR_OP( 13, sh2add, 0xffffffff, 0x00000000, 0xffffffff );
+  TEST_RR_OP( 14, sh2add, 0xfffffffd, 0xffffffff, 0x00000001 );
+  TEST_RR_OP( 15, sh2add, 0xfffffffb, 0xffffffff, 0xffffffff );
+
+  TEST_RR_OP( 16, sh2add, 0x80000003, 0x00000001, 0x7fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 );
+  TEST_RR_ZEROSRC12( 37, sh2add, 0 );
+  TEST_RR_ZERODEST( 38, sh2add, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32uzba/sh3add.S b/isa/rv32uzba/sh3add.S
new file mode 100644
index 0000000..530241e
--- /dev/null
+++ b/isa/rv32uzba/sh3add.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh3add.S
+#-----------------------------------------------------------------------------
+#
+# Test sh3add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sh3add, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sh3add, 0x00000009, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sh3add, 0x0000001f, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sh3add, 0xffff8000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  sh3add, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sh3add, 0xffff8000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP( 8,  sh3add, 0x00007fff, 0x00000000, 0x00007fff );
+  TEST_RR_OP( 9,  sh3add, 0xfffffff8, 0x7fffffff, 0x00000000 );
+  TEST_RR_OP( 10, sh3add, 0x00007ff7, 0x7fffffff, 0x00007fff );
+
+  TEST_RR_OP( 11, sh3add, 0x00007fff, 0x80000000, 0x00007fff );
+  TEST_RR_OP( 12, sh3add, 0xffff7ff8, 0x7fffffff, 0xffff8000 );
+
+  TEST_RR_OP( 13, sh3add, 0xffffffff, 0x00000000, 0xffffffff );
+  TEST_RR_OP( 14, sh3add, 0xfffffff9, 0xffffffff, 0x00000001 );
+  TEST_RR_OP( 15, sh3add, 0xfffffff7, 0xffffffff, 0xffffffff );
+
+  TEST_RR_OP( 16, sh3add, 0x80000007, 0x00000001, 0x7fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 );
+  TEST_RR_ZEROSRC12( 37, sh3add, 0 );
+  TEST_RR_ZERODEST( 38, sh3add, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uzba/Makefrag b/isa/rv64uzba/Makefrag
new file mode 100644
index 0000000..a2428f3
--- /dev/null
+++ b/isa/rv64uzba/Makefrag
@@ -0,0 +1,16 @@
+#=======================================================================
+# Makefrag for rv64uzba tests
+#-----------------------------------------------------------------------
+
+rv64uzba_sc_tests = \
+	add_uw \
+	sh1add sh1add_uw \
+	sh2add sh2add_uw \
+	sh3add sh3add_uw \
+	slli_uw \
+
+rv64uzba_p_tests = $(addprefix rv64uzba-p-, $(rv64uzba_sc_tests))
+rv64uzba_v_tests = $(addprefix rv64uzba-v-, $(rv64uzba_sc_tests))
+rv64uzba_ps_tests = $(addprefix rv64uzba-ps-, $(rv64uzba_sc_tests))
+
+spike_tests += $(rv64uzba_p_tests) $(rv64uzba_v_tests)
diff --git a/isa/rv64uzba/add_uw.S b/isa/rv64uzba/add_uw.S
new file mode 100644
index 0000000..cd89628
--- /dev/null
+++ b/isa/rv64uzba/add_uw.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# add_uw.S
+#-----------------------------------------------------------------------------
+#
+# Test add.uw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  add.uw, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  add.uw, 0x00000002, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  add.uw, 0x0000000a, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  add.uw, 0x0000000080000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  add.uw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  add.uw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, add.uw, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, add.uw, 0x0000000080007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, add.uw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, add.uw, 0x0000000100000000, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, add.uw, 0x00000000fffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, add.uw, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, add.uw, 24, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, add.uw, 25, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, add.uw, 26, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, add.uw, 24, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, add.uw, 25, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, add.uw, 26, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, add.uw, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, add.uw, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, add.uw, 26, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, add.uw, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, add.uw, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, add.uw, 26, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, add.uw, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, add.uw, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, add.uw, 26, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, add.uw, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, add.uw, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, add.uw, 26, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, add.uw, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, add.uw, 32, 32 );
+  TEST_RR_ZEROSRC12( 37, add.uw, 0 );
+  TEST_RR_ZERODEST( 38, add.uw, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uzba/sh1add.S b/isa/rv64uzba/sh1add.S
new file mode 100644
index 0000000..1ccaf77
--- /dev/null
+++ b/isa/rv64uzba/sh1add.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh1add.S
+#-----------------------------------------------------------------------------
+#
+# Test sh1add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sh1add, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sh1add, 0x00000003, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sh1add, 0x0000000d, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sh1add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  sh1add, 0xffffffff00000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sh1add, 0xfffffffeffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  sh1add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  sh1add, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, sh1add, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, sh1add, 0xffffffff00007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, sh1add, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, sh1add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, sh1add, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, sh1add, 0xfffffffffffffffd, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, sh1add, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 );
+  TEST_RR_ZEROSRC12( 37, sh1add, 0 );
+  TEST_RR_ZERODEST( 38, sh1add, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uzba/sh1add_uw.S b/isa/rv64uzba/sh1add_uw.S
new file mode 100644
index 0000000..78b198d
--- /dev/null
+++ b/isa/rv64uzba/sh1add_uw.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh1add.uw.S
+#-----------------------------------------------------------------------------
+#
+# Test sh1add.uw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sh1add.uw, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sh1add.uw, 0x00000003, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sh1add.uw, 0x0000000d, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sh1add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  sh1add.uw, 0x0000000100000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sh1add.uw, 0x00000000ffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  sh1add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  sh1add.uw, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, sh1add.uw, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, sh1add.uw, 0x0000000100007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, sh1add.uw, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, sh1add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, sh1add.uw, 0x00000001ffffffff, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, sh1add.uw, 0x00000001fffffffd, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, sh1add.uw, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sh1add.uw, 37, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, sh1add.uw, 39, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, sh1add.uw, 39, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sh1add.uw, 37, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, sh1add.uw, 39, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, sh1add.uw, 41, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add.uw, 37, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add.uw, 39, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add.uw, 41, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add.uw, 37, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add.uw, 39, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add.uw, 41, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add.uw, 37, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add.uw, 39, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add.uw, 41, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add.uw, 37, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add.uw, 39, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add.uw, 41, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, sh1add.uw, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, sh1add.uw, 64, 32 );
+  TEST_RR_ZEROSRC12( 37, sh1add.uw, 0 );
+  TEST_RR_ZERODEST( 38, sh1add.uw, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uzba/sh2add.S b/isa/rv64uzba/sh2add.S
new file mode 100644
index 0000000..a8756bb
--- /dev/null
+++ b/isa/rv64uzba/sh2add.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh2add.S
+#-----------------------------------------------------------------------------
+#
+# Test sh2add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sh2add, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sh2add, 0x00000005, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sh2add, 0x00000013, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sh2add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  sh2add, 0xfffffffe00000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sh2add, 0xfffffffdffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  sh2add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  sh2add, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, sh2add, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, sh2add, 0xfffffffe00007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, sh2add, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, sh2add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, sh2add, 0xfffffffffffffffd, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, sh2add, 0xfffffffffffffffb, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, sh2add, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 );
+  TEST_RR_ZEROSRC12( 37, sh2add, 0 );
+  TEST_RR_ZERODEST( 38, sh2add, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uzba/sh2add_uw.S b/isa/rv64uzba/sh2add_uw.S
new file mode 100644
index 0000000..1da3a43
--- /dev/null
+++ b/isa/rv64uzba/sh2add_uw.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh2add.uw.S
+#-----------------------------------------------------------------------------
+#
+# Test sh2add.uw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sh2add.uw, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sh2add.uw, 0x00000005, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sh2add.uw, 0x00000013, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sh2add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  sh2add.uw, 0x0000000200000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sh2add.uw, 0x00000001ffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  sh2add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  sh2add.uw, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, sh2add.uw, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, sh2add.uw, 0x0000000200007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, sh2add.uw, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, sh2add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, sh2add.uw, 0x00000003fffffffd, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, sh2add.uw, 0x00000003fffffffb, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, sh2add.uw, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sh2add.uw, 63, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, sh2add.uw, 67, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, sh2add.uw, 65, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sh2add.uw, 63, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, sh2add.uw, 67, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, sh2add.uw, 71, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add.uw, 63, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add.uw, 67, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add.uw, 71, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add.uw, 63, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add.uw, 67, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add.uw, 71, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add.uw, 63, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add.uw, 67, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add.uw, 71, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add.uw, 63, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add.uw, 67, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add.uw, 71, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, sh2add.uw, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, sh2add.uw, 128, 32 );
+  TEST_RR_ZEROSRC12( 37, sh2add.uw, 0 );
+  TEST_RR_ZERODEST( 38, sh2add.uw, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uzba/sh3add.S b/isa/rv64uzba/sh3add.S
new file mode 100644
index 0000000..086e07a
--- /dev/null
+++ b/isa/rv64uzba/sh3add.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh3add.S
+#-----------------------------------------------------------------------------
+#
+# Test sh3add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sh3add, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sh3add, 0x00000009, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sh3add, 0x0000001f, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sh3add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  sh3add, 0xfffffffc00000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sh3add, 0xfffffffbffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  sh3add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  sh3add, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, sh3add, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, sh3add, 0xfffffffc00007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, sh3add, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, sh3add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, sh3add, 0xfffffffffffffff9, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, sh3add, 0xfffffffffffffff7, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, sh3add, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 );
+  TEST_RR_ZEROSRC12( 37, sh3add, 0 );
+  TEST_RR_ZERODEST( 38, sh3add, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uzba/sh3add_uw.S b/isa/rv64uzba/sh3add_uw.S
new file mode 100644
index 0000000..f07375f
--- /dev/null
+++ b/isa/rv64uzba/sh3add_uw.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh3add_uw.S
+#-----------------------------------------------------------------------------
+#
+# Test sh3add.uw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sh3add.uw, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sh3add.uw, 0x00000009, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sh3add.uw, 0x0000001f, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sh3add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  sh3add.uw, 0x0000000400000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sh3add.uw, 0x00000003ffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  sh3add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  sh3add.uw, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, sh3add.uw, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, sh3add.uw, 0x0000000400007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, sh3add.uw, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, sh3add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, sh3add.uw, 0x00000007fffffff9, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, sh3add.uw, 0x00000007fffffff7, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, sh3add.uw, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sh3add.uw, 115, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, sh3add.uw, 123, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, sh3add.uw, 117, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sh3add.uw, 115, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, sh3add.uw, 123, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, sh3add.uw, 131, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add.uw, 115, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add.uw, 123, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add.uw, 131, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add.uw, 115, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add.uw, 123, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add.uw, 131, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add.uw, 115, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add.uw, 123, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add.uw, 131, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add.uw, 115, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add.uw, 123, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add.uw, 131, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, sh3add.uw, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, sh3add.uw, 256, 32 );
+  TEST_RR_ZEROSRC12( 37, sh3add.uw, 0 );
+  TEST_RR_ZERODEST( 38, sh3add.uw, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uzba/slli_uw.S b/isa/rv64uzba/slli_uw.S
new file mode 100644
index 0000000..e60f912
--- /dev/null
+++ b/isa/rv64uzba/slli_uw.S
@@ -0,0 +1,72 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slli_uw.S
+#-----------------------------------------------------------------------------
+#
+# Test slli.uw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  slli.uw, 0x0000000000000001, 0x0000000000000001, 0  );
+  TEST_IMM_OP( 3,  slli.uw, 0x0000000000000002, 0x0000000000000001, 1  );
+  TEST_IMM_OP( 4,  slli.uw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_OP( 5,  slli.uw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_OP( 6,  slli.uw, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_OP( 7,  slli.uw, 0x00000000ffffffff, 0xffffffffffffffff, 0  );
+  TEST_IMM_OP( 8,  slli.uw, 0x00000001fffffffe, 0xffffffffffffffff, 1  );
+  TEST_IMM_OP( 9,  slli.uw, 0x0000007fffffff80, 0xffffffffffffffff, 7  );
+  TEST_IMM_OP( 10, slli.uw, 0x00003fffffffc000, 0xffffffffffffffff, 14 );
+  TEST_IMM_OP( 11, slli.uw, 0x7fffffff80000000, 0xffffffffffffffff, 31 );
+
+  TEST_IMM_OP( 12, slli.uw, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_IMM_OP( 13, slli.uw, 0x0000000042424242, 0x0000000021212121, 1  );
+  TEST_IMM_OP( 14, slli.uw, 0x0000001090909080, 0x0000000021212121, 7  );
+  TEST_IMM_OP( 15, slli.uw, 0x0000084848484000, 0x0000000021212121, 14 );
+  TEST_IMM_OP( 16, slli.uw, 0x1090909080000000, 0x0000000021212121, 31 );
+
+  TEST_IMM_OP( 50, slli.uw, 0x8000000000000000, 0x0000000000000001, 63 );
+  TEST_IMM_OP( 51, slli.uw, 0xffffff8000000000, 0xffffffffffffffff, 39 );
+  TEST_IMM_OP( 52, slli.uw, 0x0909080000000000, 0x0000000021212121, 43 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, slli.uw, 0x00000080, 0x00000001, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, slli.uw, 0, 31 );
+  TEST_IMM_ZERODEST( 25, slli.uw, 33, 20 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END