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| author | Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> | 2024-05-09 09:32:20 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-09 09:32:20 +0300 |
| commit | 29e6bc8c50efd7cb8a87667345e92529136165fc (patch) | |
| tree | 4631f987fdb0b99acca6c08eaaca85797a434f84 | |
| parent | 7dfa49bb33ac2393742232cb6f77b79ec5c9df47 (diff) | |
| parent | 7f454c3d8aefb1d90727a3db7f13ac691640a575 (diff) | |
| download | riscv-tests-29e6bc8c50efd7cb8a87667345e92529136165fc.zip riscv-tests-29e6bc8c50efd7cb8a87667345e92529136165fc.tar.gz riscv-tests-29e6bc8c50efd7cb8a87667345e92529136165fc.tar.bz2 | |
Merge pull request #549 from leesum1/trigger-fix
debug: Fix nonexistent trigger registers trap handle in entry.S
| -rwxr-xr-x | debug/programs/entry.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 09cad53..5c281a6 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -84,8 +84,9 @@ handle_reset: beq t0, t1, 1b .p2align 2 2: - # Restore mtvec + # Restore mtvec and mstatus csrw mtvec, t2 + csrwi mstatus, 0 #ifdef MULTICORE csrr t0, CSR_MHARTID |