riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	2 years
latex-based-output-refactor	modified test.py for running test cases	IIITM-Jay	15 hours
master	Merge pull request #281 from cyyself/tmp_add_mcounteren	Andrew Waterman	12 days
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	3 years
rvv	Fix config imms	Colin Schmidt	6 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	4 years
[...]


Age	Commit message	Author	Files	Lines
2014-04-29	Add vf[ls]seg(\|st)h and friendsmvp	Quan Nguyen	2	-0/+8
2014-04-03	Move stats register	Stephen Twigg	2	-3/+3
2014-04-03	Add hwacha spike header file target	Stephen Twigg	1	-1/+10
2014-03-18	Add rdcycleh etc. for RV32	Andrew Waterman	4	-45/+90
2014-03-11	Fix syntax error in generated opcodes	Andrew Waterman	2	-5/+5
2014-03-11	New FP encoding	Andrew Waterman	5	-309/+367
2014-03-06	Add fclass.{s\|d} instructions	Andrew Waterman	4	-42/+68
2014-03-02	add hwacha vfmsv instructions	Yunsup Lee	1	-1/+3
2014-02-14	Renumber uarch CSRs into custom CSR space	Andrew Waterman	2	-32/+32
2014-02-06	Reserve 16 uarch-specific read-only userspace counters	Andrew Waterman	3	-0/+56
[...]