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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-05 16:11:40 -1000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-05 16:11:40 -1000 |
| commit | adfaef00e5cd57bef0aa6a9909b4bff5b3863c40 (patch) | |
| tree | 549be77796ce6730f7f07d308383f1083b6b1e38 /riscv/decode.h | |
| parent | b09a4dc2ae8185fc53991f33d09c407526e83457 (diff) | |
| parent | bc16208aa51834aa9968af44678bedd5cdeb9d35 (diff) | |
| download | riscv-isa-sim-adfaef00e5cd57bef0aa6a9909b4bff5b3863c40.zip riscv-isa-sim-adfaef00e5cd57bef0aa6a9909b4bff5b3863c40.tar.gz riscv-isa-sim-adfaef00e5cd57bef0aa6a9909b4bff5b3863c40.tar.bz2 | |
Merge pull request #1162 from riscv-software-src/sfence
SFENCE.W.INVAL and SFENCE.INVAL.IR should check privilege mode
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index bca413e..2fd573a 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -359,7 +359,9 @@ do { \ (((reg) & ~(std::remove_cv<decltype(reg)>::type)(mask)) | (((std::remove_cv<decltype(reg)>::type)(val) * ((mask) & ~((mask) << 1))) & (std::remove_cv<decltype(reg)>::type)(mask))) #define require_privilege(p) require(STATE.prv >= (p)) -#define require_novirt() if (unlikely(STATE.v)) throw trap_virtual_instruction(insn.bits()) +#define require_novirt() (unlikely(STATE.v) ? throw trap_virtual_instruction(insn.bits()) : (void) 0) +#define require_hs_qualified(cond) (STATE.v && !(cond) ? require_novirt() : require(cond)) +#define require_privilege_hs_qualified(p) require_hs_qualified(STATE.prv >= (p)) #define require_rv64 require(xlen == 64) #define require_rv32 require(xlen == 32) #define require_extension(s) require(p->extension_enabled(s)) |