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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-04 22:23:50 -1000 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-12-05 10:07:41 -1000 |
| commit | bc16208aa51834aa9968af44678bedd5cdeb9d35 (patch) | |
| tree | c2127634b6efe9b117c339594b9bb53f8c3e0276 /riscv/decode.h | |
| parent | 263af1d153cd7cb684633a4ad631dc45b60464cf (diff) | |
| download | riscv-isa-sim-bc16208aa51834aa9968af44678bedd5cdeb9d35.zip riscv-isa-sim-bc16208aa51834aa9968af44678bedd5cdeb9d35.tar.gz riscv-isa-sim-bc16208aa51834aa9968af44678bedd5cdeb9d35.tar.bz2 | |
SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modes
See discussion on https://lists.riscv.org/g/tech-privileged/message/1213
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 0acf651..b2c16f2 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -291,6 +291,8 @@ do { \ #define require_privilege(p) require(STATE.prv >= (p)) #define require_novirt() (unlikely(STATE.v) ? throw trap_virtual_instruction(insn.bits()) : (void) 0) +#define require_hs_qualified(cond) (STATE.v && !(cond) ? require_novirt() : require(cond)) +#define require_privilege_hs_qualified(p) require_hs_qualified(STATE.prv >= (p)) #define require_rv64 require(xlen == 64) #define require_rv32 require(xlen == 32) #define require_extension(s) require(p->extension_enabled(s)) |