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| author | 4vtomat <brandon.wu@sifive.com> | 2022-04-09 02:27:40 -0700 |
|---|---|---|
| committer | 4vtomat <brandon.wu@sifive.com> | 2022-04-09 02:27:40 -0700 |
| commit | 20cd1dfe3108854a94a12f1367cedbbd71622791 (patch) | |
| tree | fa60a82f6b6f884ea5e4d9e1cbf7f0447ca7330c /riscv/decode.h | |
| parent | 1ed910b229dcdafb25364053c1ed0bbb3fa81fcf (diff) | |
| download | riscv-isa-sim-20cd1dfe3108854a94a12f1367cedbbd71622791.zip riscv-isa-sim-20cd1dfe3108854a94a12f1367cedbbd71622791.tar.gz riscv-isa-sim-20cd1dfe3108854a94a12f1367cedbbd71622791.tar.bz2 | |
Adding new macro to replace repetitive code
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index a8cac94..7dd86e3 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -880,6 +880,21 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) // vector: integer and masking operation loop // +#define INSNS_BASE(PARAMS, BODY) \ + if (sew == e8){ \ + PARAMS(e8); \ + BODY; \ + }else if(sew == e16){ \ + PARAMS(e16); \ + BODY; \ + }else if(sew == e32){ \ + PARAMS(e32); \ + BODY; \ + }else if(sew == e64){ \ + PARAMS(e64); \ + BODY; \ + } + // comparision result to masking register #define VI_VV_LOOP_CMP(BODY) \ VI_CHECK_MSS(true); \ |