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| author | Eric Gouriou <ego@rivosinc.com> | 2023-06-01 18:06:55 -0700 |
|---|---|---|
| committer | Eric Gouriou <ego@rivosinc.com> | 2023-06-19 14:30:32 -0700 |
| commit | e87038ee5e6545a5149cdf4334d220f951534f30 (patch) | |
| tree | b2224a87df4346e9f5b0909058a08e4f9be2aeef /riscv/decode.h | |
| parent | d5c0339484323b5a9498576d70ec90eab2e13438 (diff) | |
| download | riscv-isa-sim-e87038ee5e6545a5149cdf4334d220f951534f30.zip riscv-isa-sim-e87038ee5e6545a5149cdf4334d220f951534f30.tar.gz riscv-isa-sim-e87038ee5e6545a5149cdf4334d220f951534f30.tar.bz2 | |
Zvk: Implement Zvbb, Vector Bit-manipulation for Cryptography
Implement the proposed instructions in Zvbb:
- vandn.{vv,vx}, vector bitwise and-not
- vbrev.v, vector bit reverse in element
- vbrev8.v, vector bit reverse in bytes
- vrev8.v, vector byte reverse
- vctz.v, vector count trailing zeros
- vclz.v, vector count leading zeros
- vcpop.v, vector population count
- vrol.{vv,vx}, vector rotate left
- vror.{vi,vv,vx}, vector rotate right
- vwsll.{vi,vv,vx} vector widening shift left logical
A new instruction field, 'zimm6', is introduced, encoded
in bits [15, 19] and [26].. It is used by "vror.vi" to encode
a shift immediate in [0, 63].
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index dad32a1..cd1c0a1 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -140,6 +140,7 @@ public: uint64_t v_vta() { return x(26, 1); } uint64_t v_vma() { return x(27, 1); } uint64_t v_mew() { return x(28, 1); } + uint64_t v_zimm6() { return x(15, 5) + (x(26, 1) << 5); } uint64_t p_imm2() { return x(20, 2); } uint64_t p_imm3() { return x(20, 3); } |